• Journal of Korean Society of Industrial and Systems Engineering
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• v.20 no.41
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• pp.177-188
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• 1997

This study describes the important information for establishing Human Computer Interface System for solving the large scale Traveling Saleman Problem in Printed Circuit Board production. Appropriate types and sizes of partitioning of large scale problems are discussed. Optimal tours for the special patterns appeared in PCB's are given. The comparision of optimal solutions of non-Euclidean problems and Euclidean problems shows the possibilities of using human interface in solving the Chebyshev TSP. Algorithm for the large scale problem using described information and coputational result of the practical problem are given.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1068-1073
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• 1987

Traditional circuit partitioning algorithm using the cluster development method, which is suitable for such applications as single chip floor planning or multiple layer PCB system placement, where the clusters are formed so that inter-cluster nets are localized within the I/O connector pins, may not be appropriate for the functiona block placement in truly 3-D electronic modules. 3-D hybrid IC is one such example where the inter-layer routing as well as the intra-layer routing can be maximally incorporated to reduce the overall circuit size, cooling requirements and to improve the speed performance. In this paper, we propose a new algorithm called MBE(Minimum Box Embedding) for the layer assignment of each functional block in 3-D hybrid IC design. The sequence of MBE is as follows` i) force-directed relaxation in 3-D space, ii) exhaustive search for the optimal orientation of the slicing plane and iii) layer assignment. The algorithm is first explaines for a 2-D reduced problem, and then extended for 3-D applications. An example result for a circuit consisting of 80 blocks has been shown.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.961-968
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• 2018

Recently, researches on automatic recognition of human activities have been actively carried out with the emergence of various intelligent systems. Since a large amount of visual data can be secured through Closed Circuit Television, it is required to recognize human behavior in a dynamic situation rather than a static situation. In this paper, we propose new intelligent human activity recognition model using the trajectory information extracted from the video sequence. The proposed model consists of three steps: segmentation and partitioning of trajectory step, feature extraction step, and behavioral learning step. First, the entire trajectory is fuzzy partitioned according to the motion characteristics, and then temporal features and spatial features are extracted. Using the extracted features, four pedestrian behaviors were modeled by decision tree learning algorithm and performance evaluation was performed. The experiments in this paper were conducted using Caviar data sets. Experimental results show that trajectory provides good activity recognition accuracy by extracting instantaneous property and distinctive regional property.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1724-1727
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• 2002

Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.22-33
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• 1999

In this paper, we propose a new multi-way circuit partitioning system that partition large circuits to progrmmable circuit board which consist of FPGAs and interconnect components. Here the routing topology among the chips are predetermined and the number of available interconnections are fixed. Since the given constraints are difficult to be satisfied by the previous partition method, we suggest a new multi-way partition method by target restriction that considers all the constraints for the given board. To speed up, we construct a multi-level cluster tree for hierarchical partitioning. Experimental results for several benchmarks show that the our partition method partition them by satisfying all the given constraints and it used up to 10 % fewer interconnections among the chips than the previous K-way partition method.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.811-814
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• 1998

REcent research about current testing($\textrm{I}_{DDQ}$ testing) has been emphasizing that $\textrm{I}_{DDQ}$ testing in addition to the logical voltage testing is necessary to increase the fault coverage. The $\textrm{I}_{DDQ}$. testing can detect physical faults other than the classical stuck-at type fault, which affect reliability. One of the most critical issues in the $\textrm{I}_{DDQ}$ testing is to insert a built-in current sensor (BICS) that can detect abnormal static currents from the power supply or to the ground. This paper presents a new BICS for internal current testing for large CMOS logic circuits. The proposed BICS uses a single phase clock to minimize the hardware overhead. It detects faulty current flowing and converts it into a corresponding logic voltage level to make converts it into a corresponding logic voltage level to make it possible to use the conventional voltage testing techniqeus. By using current mirroring technique, the proposed BICS can work at very high speed. Because the proposed BICS almost does not affects normal operation of CUT(circuit under test), it can be used to a very large circuit without circuit partitioning. By altenating the operational modes, a circuit can be $\textrm{I}_{DDQ}$-tested as a kind of self-testing fashion by using the proposed BICS.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.82-89
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• 1993

In this paper, we proposed the autonomous algorithm of pseudo-exhaustive testing for the multi-level combinational logic circuits. For the processing of shared-circuit that existed in each cone-circuit when it backtracked the path from PO to PI of CUT at the conventional verification testing, the dependent relation of PI-P0 is presented by a dependence matrix so it easily partitioned the sub-circuits for the pseudo-exhaustive testing. The test pattern of sub-circuit's C-inputs is generated using a binary counter and the test pattern of I-inputs is synthesized using a singular cover and consistency operation. Thus, according to the test patterns presented with the recipe cube, the number of test pattrens are reduced and it is possible to test concurrently each other subcircuits. The proposed algorithm treated CUT's net-list to the source file and was batch processed from the sub-circuit partitioning to the test pattern generation. It is shown that the range of reduced ration of generated pseudo-exhaustive test pattern exhibits from 85.4% to 95.8% when the average PI-dependency of ISACS bench mark circuits is 69.4%.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1061-1064
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• 1998

This paper proposes a new topology-based partition method for reconfigurable FPGA systems whose components nd the number of interconnections are predetermined. Here, the partition problem must also consider nets that pass through components such as FPGAs and routing devices to route 100%. We formulate it as a quadratic boolean programming problem suggest a paritition method for it. Experimental results show 100% routing, and up to 15% improvement in the maximum number of I/O pins.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10a
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• pp.586-588
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• 2001

회로분할 기법은 VLSI 설계뿐만 아니라 많은 분야에서 응용될 수 있어 오랫동안 연구가 행해졌다. 대부분의 회로분할 휴리스틱에서 Fiduccia-Mattheyses(FM) 방법을 핵심 기술로 사용하고 있다. 회로 분할 문제는 또한 다른 컴비네토리얼 문제에서처럼 해 공간에서 최적해를 찾는 문제로 볼 수 있는데. GWW(Go With the Winners) 방법은 해 공간을 검색하는 성공적인 패러다임 중의 하나이다. 본 논문에서는 “GWW” 패러다임을 FM 방법에 접목시켜 회로를 분할하기 위한 휴리스틱을 제안한다. MCNC 벤치마크 회로를 이용하여 전형적인 FM 방법에 의한 결과와 “GWW”패러다임을 접목하여 얻은 결과를 비교하였다. 실험결과는 매우 고무적이다.