• Journal of IKEEE
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• v.17 no.3
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• pp.324-331
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• 2013

In this paper, we implemented memristor emulator circuit on Printed Circuit Board (PCB) and observed the inherent pinched hysteresis characteristic of memristors by measuring the emulator circuit on PCB. The memristor emulator circuit implemented on PCB is composed of simple discrete devices not using any complicated circuit blocks thus we can integrate the memristor emulator circuits in very small layout area on Silicon substrate. The programmable gain amplifier is designed using the proposed memristor emulator circuit and verified that the amplifier's voltage gain can be controlled by programming memristance of the emulator circuit by circuit simulation. Threshold switching is also realized in the proposed emulator circuit thus memristance can remain unchanged when the input voltage applied to the emulator circuit is lower than VREF. The memristor emulator circuit and the programmable gain amplifier using the proposed circuit can be useful in teaching the device operation, functions, characteristics, and applications of memristors to students when thet cannot access to device and fabrication technologies of real memristors.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.4
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• pp.33-39
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• 2014

In this paper, a new on-chip aging sensing circuit based on flip-flops is proposed to detect a circuit failure of MOSFET digital circuits casued by aging phenomenon such as HCI and BTI. The proposed circuit uses timing windows to warn against a guardband violation of sequential circuits, and generates three warning bits right before circuit failures occur. The generated bits can apply to an adaptive self-tuning method for reliable system design as control signals. The aging sensor circuit has been implemented using 0.11um CMOS technology and evaluated by $4{\times}4$ multiplier with power gating structure.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.77-84
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• 1998

A voltage controlled chaotic circuit has been designed in integrated circuit and fabricated by using 0.8$\mu\textrm{m}$ single poly CMOS technology. The fabricated chaotic circuit consist of sample and hold circuits, op-amps, nonlinear function generator and two phase clock generator. The test results of the chaotic circuit show that periodic state, quasi-periodic state and chaotic state can be obtained according to the input control voltage with the ${\pm}$2.5V power supply and clock rate of 20kHz. In addition, two dimensional chaotic patterns have been observed by connecting this circuit in parallel or series

• Journal of Practical Engineering Education
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• v.9 no.2
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• pp.99-106
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• 2017

The most important thing in STEAM education is to enhance students' interest and understanding of science and technology. In this paper, we propose basic circuit system design and control method applicable to STEAM fusion education. The circuit system design practice using the breadboard is designated as an essential curriculum in the corresponding department at the high school and college level in the domestic curriculum. However, there is a lack of STEAM convergence implementation examples that can easily understand circuit system design and control methods. Therefore, we proposed and tested a method to implement and control a media art type circuit system.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.143-148
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• 1998

The Design criteria of the auxiliary resonant snubber inverter (ARSI) using a load-side circuit are discussed in relation to electric propulsion drives. In this regard, this paper attempts to develop a set of design criteria for the ARSI. First, the switching characteristics of IGBTs under soft-switching mainly in terms of dv/dt/, di/dt and switching losses are discussed and utilized for optimizing the selection of the resonant components in the system. After that, the proper control strategies of ARSIs are analyzed and simulated based on voltage space vector modulations. Later, the design, control and implementation of the auxiliary resonant circuit suitable for industrial products are analyzed and presented. And finally, other factors including power stage layout, packaging and the choice of current sensors are included. The detailed simulation and experimental results will be included based on a laboratory prototype. The proposed design criteria of the ARSI would help the implementation of an electric propulsion drive system.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.97-102
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• 2001

In computer-aided design, partitioning is task of clustering objects into groups to that a given objection function is optimized It is used at the layout level to fin strongly connected components that can be placed together in order to minimize the layout area and propagation delay. Partitioning can also be used to cluster variables and operation into groups for scheduling and unit selection in high-level synthesis. The most popular algorithms partitioning include the Kernighan-Lin algorithm Fiduccia-Mattheyses heuristic and simulated annealing In this paper we propose a genetic algorithm searching solution space for the circuit partitioning problem. and then compare it with simulated annealing by analyzing the results of implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.740-749
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• 2015

In the visible light (VL) communication based on the conventional LED lights, depending on the increase of the communication range, the signal received at the photodiode of the VL receiver has usually the random distorted and decreased amplitude due to the path loss and fading effects of the VL channel. In order to overcome this problem, we propose, design, and implement the visible light communication circuit based on the comparator threshold voltage, where has a built-in distance compensation function. In addition, the performance of the proposed technique is evaluated and analyzed depending on the distance and communication speed through comparing the proposed VLC system based on the threshold voltage with the conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.980-986
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• 2002

In the fast data communication system, synchronized by a clock source, the loss of data will often occur due to several reasons as a differential routing path between data and clock, a differential propagation delay of components or an unstable phase of clock and data by external noise. In this paper, we describe the ASIC implementation of the data compensation circuit which can detect the data loss from above problems and recovery to original data with stable synchronization. Especially it supports a strong stability and a good BER in the communication system for fast data transfer as optic area. This circuit is implemented by Verilog HDL and available to the digital ASIC implementations related to fast data transfer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1872-1879
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• 1994

The design and implementation of Ku-Band frequency synthesizer was accomplished by the use of PLL and frquency multiple method. Design procedure and operation characteristics of PLL circuit were analyzed on the basis of control theory to synthesize about 1 GHz frequency which should be stable. By connecting frequency doubler and frequency eighth multiplier to the designed PLL circuit in series, Ku-Band frequency was synthesized. The validity of design method of Ku-Band frequency synthesizer was verified through experimental results.