• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.197-199
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• 2012

Recently, a lot of general-purpose application programs in addition to graphic applications have been parallelized for boosting their performance using Graphic Processing Unit (GPU)'s excellent floating-point performance. In order to maximize the application performance on GPUs, optimizing the memory hierarchy and the on-chip caches such as the shared memory is essential. In this paper, we propose techniques to optimize the shared memory, and verify its effectiveness using a pattern matching application program.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Journal of Sensor Science and Technology
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• v.17 no.1
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• pp.15-22
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• 2008

When designing image sensors including a CMOS vision chip for edge detection, resolution is a significant factor to evaluate the performance. It is hard to improve the resolution of a bio-inspired CMOS vision using a resistive network because the vision chip contains many circuits such as a resistive network and several signal processing circuits as well as photocircuits of general image sensors such as CMOS image sensor (CIS). Low resolution restricts the use of the application systems. In this paper, we improve the resolution through layout and circuit optimization. Furthermore, we have designed a printed circuit board using FPGA which controls the vision chip. The vision chip for edge detection has been designed and fabricated by using $0.35{\mu}m$ double-poly four-metal CMOS technology, and its output characteristics have been investigated.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.103-105
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• 2003

COG (Chip on Glass) technology using solder bump reflow has been investigated to attach IC chip directly on glass substrate of LCD panel. As It chip and LCD panel have to be heated to reflow temperature of the so]der bumps for COG bonding, it is necessary to use low-temperature solders to prevent the damage of liquid crystals of LCD panel. In this study, using the Sn-52In solder bumps of $40{\mu}m$ pitch size, solder joints between Si chip and glass substrate were made at temperature below $150^{\circ}C$. The contact resistance of the solder joint was $8.58m\Omega$, which was much lower than that of the joint made using the conventional ACF bonding technique. The Sn-52In solder joints with underfill showed excellent reliability at a hot humid environment.

• Transactions of Materials Processing
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• v.12 no.4
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• pp.358-363
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• 2003

Adiabatic shear bands have been observed in the serrated chip during high strain rate metal cutting process of medium carbon steel and titanium alloy The recent microscopic observations have shown that dynamic recrystallization occurs in the narrow adiabatic shear bands. However the conventional flow stress models such as the Zerilli-Armstrong model and the Johnson-Cook model, in general, do not predict the occurrence of dynamic recrystallization (DRX) in the shear bands and the thermal softening effects accompanied by DRX. In the present study, a strain hardening and thermal softening model is proposed to predict the adiabatic shear localized chip formation. The finite element analysis (FEA) with this proposed flow stress model shows that the temperature of the shear band during cutting process rises above 0.5Τ$_{m}$. The simulation shows that temperature rises to initiate dynamic recrystallization, dynamic recrystallization lowers the flow stress, and that adiabatic shear localized band and the serrated chip are formed. FEA is also used to predict and compare chip formations of two flow stress models in orthogonal metal cutting with AISI 1045. The predictions of the FEA agreed well with the experimental measurements.s.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.190-195
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• 2005

The hearing aid chip described in this paper is an analog & digital mixed system. The design focuses on the$\mu$DSP core. This $\mu$DSP core includes internal time delays to two inputs from front and rear microphones. The paper consists of two parts; one is the composure and signal processing algorithm of digital hearing aids and the other is Verilog HDL codes for$\mu$DSP cores. All digital modules in the design were coded and synthesized by Verilog HDL codes which were verified by Mentor Graphics and Synopsis semiconductor chip design tools.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.101-106
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• 2001

In order to establish the optimum process parameters and diamond saw blade composition for machining natural stone, the chip formation process and the wear process must be understood. Diamond saw blade is one of the most effective, versatile, and extensively used methods of processing rock and other hard materials, such as granite, marble, concrete and asphalt. For many years, it has been known that chip thickness is one of the most significant in the understanding of the sawing process, and other variables such as force and power have been correlated with it. In this study, mathematical relations of a material chipped by a single grit of the saw blade will be undertaken. The material chipping geometries have been mathematically defined and derived as maximum chip thickness.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.253-256
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• 2001

This paper describes a high speed MAC(Media Access Control) function chip for IEEE 802.11 MAC layer protocol. The MAC chip has control registers and interrupt scheme for interface with CPU and deals with transmission/reception of data as a unit of frame. The developed MAC chip is composed of protocol control block, transmission block, and reception block which supports the BCF function in IEEE 802.11 specification. The test suite which is adopted in order to verify operation of the MAC chip includes various functions, such as RTS-CTS frame exchange procedure, correct IFS(Inter Frame Space)timing, access procedure, random backoff procedure, retransmission procedure, fragmented frame transmission/reception procedure, duplicate reception frame detection, NAV(Network Allocation Vector), reception error processing, broadcast frame transmission/reception procedure, beacon frame transmission/reception procedure, and transmission/reception FIEO operation. By using this technique, it is possible to reduce the load of CPU and firmware size in high speed wireless LAN system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.602-605
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• 2000

Recently, a study of intellectual smell recognition system is applied for the various fields such as control of food processing and survey of decay. A basic gas recognition system was implemented gases using four metal oxides semiconductor sensors as inputs. A CPLD chip of twenty thousand gates level was used for this purpose. The CPLD chip was designed and the availability of the one chip smell recognition system was tested.

• Nuclear Engineering and Technology
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• v.55 no.3
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• pp.1015-1020
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• 2023

A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.