• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2861-2873
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• 1997

An FPU(Floating Point unit) is the principle component in high performance computer and is placed on a chip together with main processing unit recently. As a Processing speed of the FPU is accelerated, the rounding stage, which occupies one of the floating point Processing steps for floating point operations, has a considerable effect on overall floating point operations. In this paper, by studying and analyzing the processing flows of the conventional floating point adder/subtractor, multipler and divider, which are main component of the FPU, efficient rounding mechanisms are presented. Proposed mechanisms do not require any additional execution time and any high speed adder for rounding operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

• Journal of the Korea Society of Computer and Information
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• v.23 no.1
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• pp.33-39
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• 2018

In this paper, We studied the possibility of SoC(System On Chip) design using infrared image processing IP(Intellectual Property). And, we studied NUC(Non Uniformity Correction), BPR(Bad Pixel Recovery), and CEM(Contrast Enhancement) processing, the infrared image processing algorithm implemented by IP. We showed the logic and timing diagram implemented through the hardware block designed based on each algorithm. Each algorithm was coded as RTL(Register Transfer Level) using Verilog HDL(Hardware Description Language), ALTERA QUARTUS synthesis, and programed in FPGA(Field Programmable Gated Array). In addition, we have verified that the image data is processed at each algorithm without any problems by integrating the infrared image processing algorithm. Particularly, using the directly manufactured electronic board, Processor, SRAM, and FLASH are interconnected and tested and the verification result is presented so that the SoC type can be realized later. The infrared image processing IP proposed and verified in this study is expected to be of high value in the future SoC semiconductor fabrication. In addition, we have laid the basis for future application in the camera SoC industry.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.1
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• pp.58-62
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• 2007

Digital communication is important for reliability and mobilization of the multi-channel communication systems. Transmitting and receiving data for the mobilization should be possible in anywhere and in anytime. And this system must be designed light weight small size and low power. One are essential technology for implementing the mobile wireless communication system on the age of ubiquotos. Requirements in constructing such communication field are followings. At first data transmitting and receiving should be carried out by a simple command. Second, the device should be designed as hand-hold type and low power consumption. Third, data communication should be reliable. As one of examples, car to car system which is popular in the market is introduced here, All traffic information in highway is transmitted from one car to another by using this system which can prevent possible traffic accident. This paper shows the design of a digital data communication system with CC1020 chip. This CC1020 makes easy frequency selection and easy switch from the transmit mode to the receive mode by simple setting of a memory register in the chip. The transmit power of this system is designed 10dBm and its communication range is about 100m. The power supplied this system is 3V considered as low power. The sleep mode can be easily entered during transmit mode or receive mode. We shows the program algorithm of CC1020 and interface circuit between MCU and CC1020. We shows the Photo of the CC1020 Module and Atmega128 Module.. We analysed the receiver rate with this system.

• Korean Journal of Environmental Agriculture
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• v.35 no.4
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• pp.247-255
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• 2016

BACKGROUND: Acrylamide (CAS No. 79-06-1) is known to be a carcinogenic compound, and is classified as a Group 2A compound by the International Agency for Research on Cancer (IARC, 1994). Acrylamide can be generated during the browning process via the non-enzymatic Maillard reaction of carbohydrates such as reducing sugars and of amino acids such as asparagine, both of which occur at a temperature above $120^{\circ}C$. Potato tubers contain reducing sugars, and thus, this will affect the safety of processed potato products such as potato chips and French fries. In order to reduce the level of acrylamide in potato processed products, it is therefore necessary to understand factors that affect the reducing sugar content of potatoes, such as environmental factors and potato storage conditions, as well as understanding factors affecting acrylamide formation during potato processing itself. METHODS AND RESULTS: Potatoes were cultivated in eight regions of Korea; For each of these different environments, soil physico-chemical characteristics such as pH, electrical conductivity, total nitrogen, available phosphate, and exchangeable cation content were measured and correlations with potato reducing sugar content and potato chip acrylamide levels were examined. The reducing sugar content in potato during storage for three months was determined and acrylamide level in potato chip was analyzed after processing. The storage temperature levels were $4^{\circ}C$, $8^{\circ}C$, or $10^{\circ}C$, respectively. The acrylamide content of chips prepared from potatoes stored at $10^{\circ}C$ or $20^{\circ}C$ for one month was analyzed and the different frying times were 2, 3, 5, and 7 min. CONCLUSION: This study showed that monitoring and controlling the phosphate content within a potato field should be sufficient to avoid producing brown or black potato chips. For potatoes stored at low temperatures, a reconditioning period ($20^{\circ}C$ for 20 days) is required in order to reduce the levels of reducing sugars in the potato and subsequently reduce the acrylamide and improve chip coloration and appearance.

• Resources Recycling
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• v.31 no.4
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• pp.34-39
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• 2022

In this study, effects of ultrasonic energy on the cementation reaction and copper recovery rate were investigated for different types of iron samples, such as plate, chip, and powder, for recovering copper from waste etchant, which contained ~3.5% copper. The cementation reaction using the ultrasonic energy was more effective than the simple stirring reaction, with the former exhibiting a high copper recovery rate than the latter for the same time interval. When cementation was performed for 25 min with ultrasonic treatment, rather than simple stirring, the copper recovery rate of the plate, chip, and powder improved from 7.0% to 12.0%, 14.0% to 46.1%, and 41.9% to 77.2%, respectively. Therefore, the use of ultrasonic energy could detach the copper recovered by the cementation reaction from the surface of the iron samples, thereby increasing the copper recovery rate. Owing to the use of ultrasonic energy, the copper recovery rate increased by 2-6 times, and the recovered copper exhibited a decreased particle size compared to that obtained via simple stirring.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.11a
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• pp.149-152
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• 2007

본 논문은 바이오 인포메틱스의 분야를 간단히 소개하고 기능유전체학에서 microarray 실험에 대한 통계적 방법론을 살펴보고자 한다. 또한 DNA chip 설계와 생물학적 특정에 대해 살펴보고 각 분야에서 적용되는 통계적 방법을 연구분석 해보고자 한다.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.691-693
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• 1998

A parallel processing systolic array reduces execution time of the Back-propagation ANN. But, systolic array must be designed whenever the number of neurons in the ANN differ. To use the systolic array which is aready designed ad a fixed size VLSI chip, partition of the problem size systolic array must be performed. This paper presents a design method of the fixed size systolic array for the Back-propagation algorthm using LSGP and LPGS partion method

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.217-220
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• 2000

In this paper, A low-power MOS monolithic peak detector is presented. Designed for monolithic and low-power characteristics, this MOS peak detector can be integrated easily on the same chip as a module of large communication systems. The simulation results of this peak detector which was composed with four NMOSs and two capacitors show the power dissipation of 0.972㎽ and the good operations for 2㎓ operating pulse frequency. Therefore, it may be used as a functional block for various signal processing systems.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.1
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• pp.107-114
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• 1994

Hardware implementation of the on-chip learning artificial neural networks is important for real-time processing. A pRAM model is based on probabilistic firing of a biological neuron and can be implemented in the VLSI circuit with learning capability. We derive a backpropagation learning algorithm for the pRAM networks and present its circuit implementation with stochastic computation. The simulation results confirm the good convergence of the learning algorithm for the pRAM networks.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.3
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.