Design of the Fixed Size Systolic Array for the Back-propagation ANN

역전파 ANN을 위한 고정 크기 시스톨릭 어레이 설계

  • 김지연 (계명대학교 컴퓨터 및 전자공학부) ;
  • 장명숙 (계명대학교 컴퓨터 및 전자공학부 박사후 연구원) ;
  • 박기현 (계명대학교 컴퓨터 및 전자공학부)
  • Published : 1998.10.01

Abstract

A parallel processing systolic array reduces execution time of the Back-propagation ANN. But, systolic array must be designed whenever the number of neurons in the ANN differ. To use the systolic array which is aready designed ad a fixed size VLSI chip, partition of the problem size systolic array must be performed. This paper presents a design method of the fixed size systolic array for the Back-propagation algorthm using LSGP and LPGS partion method

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