• Title/Summary/Keyword: channel decoder

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Performance Evaluations on Shared-Type Encoder/Decoder with Wavelength/Time 2-D Codes for Optical CDMA Networks (파장/시간의 2차원 코드를 사용한 광 부호 분할 다중 접속 부호기/복호기의 성능 분석)

  • Hwang, Hu-Mor;Chang, Chul-Ho;Song, Jin-Ho
    • Proceedings of the KIEE Conference
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    • 2006.07d
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    • pp.2013-2014
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    • 2006
  • For large capacity optical CDMA networks, we propose a shared-type encoder/decoder based on an tunable wavelength conveter (TWC) and an arrayed waveguide grating (AWG) router. Feasibility of the structure of the proposed encoder/decoder for dynamic code allocation is tested through simulations using three types of wavelength/time 2-D codes, which are the generalized multi-wavelength prime code(GMWPC), the generalized multi-wavelength Reed-Solomon code(GMWRSC) and the matrix code. Test results show that the proposed encoder/decoder can increase the channel efficiency not only by increasing the number of simultaneous users without any multiple-access interference but by using a relatively short length CDMA codes.

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A Implementation of Simple Convolution Decoder Using a Temporal Neural Networks

  • Chung, Hee-Tae;Kim, Kyung-Hun
    • Journal of information and communication convergence engineering
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    • v.1 no.4
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    • pp.177-182
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    • 2003
  • Conventional multilayer feedforward artificial neural networks are very effective in dealing with spatial problems. To deal with problems with time dependency, some kinds of memory have to be built in the processing algorithm. In this paper we show how the newly proposed Serial Input Neuron (SIN) convolutional decoders can be derived. As an example, we derive the SIN decoder for rate code with constraint length 3. The SIN is tested in Gaussian channel and the results are compared to the results of the optimal Viterbi decoder. A SIN approach to decode convolutional codes is presented. No supervision is required. The decoder lends itself to pleasing implementations in hardware and processing codes with high speed in a time. However, the speed of the current circuits may set limits to the codes used. With increasing speeds of the circuits in the future, the proposed technique may become a tempting choice for decoding convolutional coding with long constraint lengths.

A Convolutional Decoder using a Serial Input Neuron

  • Kim, Kyunghun;Lee, Chang-Wook;Jeon, Gi-Joon
    • 제어로봇시스템학회:학술대회논문집
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    • 2002.10a
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    • pp.89.1-89
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    • 2002
  • Conventional multilayer feedforward artificial neural networks are very effective in dealing with spatial problems. To deal with problems with time dependency, some kinds of memory have to be built in the processing algorithm. In this paper we show how the newly proposed Serial Input Neuron (SIN) convolutional decoders can be derived. As an example, we derive the SIN decoder for \ulcornerrate code with constraint length 3. The SIN is tested in Gaussian channel and the results are compared to the results of the optimal Viterbi decoder. A SIN approach to decode convolutional codes is presented. No supervision is required. The decoder lends itself to pleasing implementations in hardware and processing...

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Low Complexity Decoder for Space-Time Turbo Codes

  • Lee Chang-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.4C
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    • pp.303-309
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    • 2006
  • By combining the space-time diversity technique and iterative turbo codes, space-time turbo codes(STTCS) are able to provide powerful error correction capability. However, the multi-path transmission and iterative decoding structure of STTCS make the decoder very complex. In this paper, we propose a low complexity decoder, which can be used to decode STTCS as well as general iterative codes such as turbo codes. The efficient implementation of the backward recursion and the log-likelihood ratio(LLR) update in the proposed algorithm improves the computational efficiency. In addition, if we approximate the calculation of the joint LLR by using the approximate ratio(AR) algorithm, the computational complexity can be reduced even further. A complexity analysis and computer simulations over the Rayleigh fading channel show that the proposed algorithm necessitates less than 40% of the additions required by the conventional Max-Log-MAP algorithm, while providing the same overall performance.

Trellis-coded .pi./4 shift QPSK with sliding multiple symbol detection흐름 다중심벌검파를 적용한 트렐리스 부호화된 .pi./4 shift QPSK

  • 전찬우;박이홍;김종일
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.2
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    • pp.483-494
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    • 1996
  • In this paper, we proposed the receive decoder and Virterbi algorithm with sliding multiple symbol detection using MLSE. the informationis transmitted by the phase difference of the adjacent channel signal at the .pi./4 shift QPSK. In order to apply the .pi./4 shift QPSK to TCM, we use the signal set expansion and the signal set partition by the phase differences. And the Viterbi decoder containing branch mertrice of the squared Euclidean distance of the first, second and Lth order phase difference is introduced in order to extract the information in the differential detection of the Trellis-Coded .pi./4 shift QPSK. The proposed Viterbi decoder and receiver are conceptually same to the sliding multiple symbol detection method using the MLSE. By uisng this method, the study shows that the Trellis-Coded .pi./4 shift QPSK is an attractive scheme for the power and the bandimited systems while also improving the BER performance when the Viterbi decoder is employed to the Lth order phase difference metrics.

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VLSI Design of Soft Decision Viterbi Decoder Using Systolic Array Architecture (역추적 방식의 시스토릭 어레이 구조를 가진 연판정 비터비 복호기의 설계)

  • Kim, Ki-Bo;Kim, Jong-Tae
    • Proceedings of the KIEE Conference
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    • 1999.07g
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    • pp.3199-3201
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    • 1999
  • Convolutional coding with Viterbi decoding is known as a powerful method for forward error correction among many kinds of channel coding methods. This paper presents a soft decision Viterbi decoder which has systolic array trace-back architecture[1]. Soft decision is known as more effective method than hard decision and most of digital communication systems use soft decision. The advantage of using a systolic array decoder is that the trace-back operation can be accomplished continuously in an array of registers in a pipe-line fashion, instead of waiting for the entire trace-back procedure to be completed at each iteration. Therefore it may be suitable for faster communication system. We described operations of each module of the decoder and showed results of the logic synthesis and functional simulation.

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VLSI Design of EPR-4 Viterbi Decoder for Magnetic Disk Read Channel (자기 디스크 출력 채널용 EPR-4 비터비 디코더의 VLSI 설계)

  • ;Bang-Sup Song
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.7A
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    • pp.1090-1098
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    • 1999
  • In this paper ERP-4 viterbi decoder for magnetic disk read channel is designed. The viterbi decoder consists of ACS circuit, path memory circuit, minimum detection circuit, and output selection circuit. In the viterbi decoder the number of state is reduced from 8 to 6 using (1,7) RLL codes and modulo comparison based on 2's complement arithmetic is applied to handle overflow problem of ACS module. Also to determine the correct symbol values in nonconvergent condition of path memory, pipelined minimum detector which determines path with minimum state metric is used. The EPR-4 viterbi decoder is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology and consists of about 15,300 transistors and has 250 Mbps data rates under 3.3 volts.

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Symbol Decoding Schemes Combined with Channel Estimations for Coded OFDM Systems in Fading Channels. (페이딩 채널환경에서 CDFDM 시스템에 대한 채널 추정과 결합된 심볼검출 방법)

  • Cho, Jin-Woong;Kang, Cheol-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.9
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    • pp.1-10
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    • 2000
  • This paper proposes symbol decoding schemes combined with channel estimation techniques for coded orthogonal frequency division multiplexing (COFDM) systems in fading channels. sThe proposed symbol decoding schemes are consisted of a symbol decoding technique and channel estimation techniques. The symbol decoding based on Viterbi algorithm is achieved by matching the length of branch word from encoder trellis to the codeword length of symbol candidate on decoder trellis. Three combination schemes are described and their error performances are compared. The first scheme is to combine a symbol decoding technique with a training channel estimation technique. The second scheme joins a decision directed channel estimation technique to the first scheme. The time varying channel transfer functions are tracked by the decision directed channel estimation technique and the channel transfer functions used in the symbol decoder are updated every COFDM symbol. Finally, In order to reduce the effect of additive white Gaussian noise (AWGN) between adjacent subchannels, deinterleaved average channel estimation technique is combined. The error performances of the three schemes are significantly improved being compared with that of zero forcing equalizing schemes.

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Design of Joint Source-Channel Coder for H.263+ by MAP estimation (H.263+을 위한 MAP기반의 Joint Source-Channel Coder 설계)

  • 송호현;최윤식
    • Proceedings of the IEEK Conference
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    • 2000.11d
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    • pp.171-174
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    • 2000
  • In this paper, We try to design combined source-channel coder that is compatible with video coding standards. This MAP decoder is proposed by adding semantic structure and semantic constraint of video coding standards to the method using redundnacy of the MAP decoders proposed previously. Then, We get the better performance than usual channel coder's.

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Channel Error Detwction and Concealment Technqiues for the MPEG-2 Video Standard (MPEG-2 동영상 표준방식에 대한 채널 오차의 검출 및 은폐 기법)

  • 김종원;박종욱;이상욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.10
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    • pp.2563-2578
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    • 1996
  • In this paper, channel error characteristics are investigated to alleviate the channel error propagation problem of the digital TV transmission systems. First, error propagation problems, which are mainly caused by the inter-frame dependancy and variable length coding of the MPEG-2 baseline encoder, are intensively analyzed. Next, existing channel resilient schemes are systematically classified into two kinds of schemes; one for the encoder and the other for the decoder. By comparing the performance and implementation cost, the encoder side schemes, such as error localization, layered coding, error resilience bit stream generation techniques, are described in this paper. Also, in an effort to consider the parcticality of the real transmission situation, an efficient error detection scheme for a decoder system is proposed by employing a priori information of the bit stream syntas, checking the encoding conditions at the encoder stage, and exploiting the statistics of the image itself. Finally, subsequent error concealment technique based on the DCT coefficient recovery algorithm is adopted to evaluate the performance of the proposed error resilience technique. The computer simulation results show that the quality of the received image is significantly improved when the bit error rate is as high as 10$^{-5}$ .

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