The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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VLSI Design of EPR-4 Viterbi Decoder for Magnetic Disk Read Channel

자기 디스크 출력 채널용 EPR-4 비터비 디코더의 VLSI 설계

  • ;
  • Bang-Sup Song (Dept. of Electrical and Computer Engineering, University of Illinois)
  • 최병윤 (동의대학교 컴퓨터공학과 정회원) ;
  • Published : 1999.07.01
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Abstract

In this paper ERP-4 viterbi decoder for magnetic disk read channel is designed. The viterbi decoder consists of ACS circuit, path memory circuit, minimum detection circuit, and output selection circuit. In the viterbi decoder the number of state is reduced from 8 to 6 using (1,7) RLL codes and modulo comparison based on 2's complement arithmetic is applied to handle overflow problem of ACS module. Also to determine the correct symbol values in nonconvergent condition of path memory, pipelined minimum detector which determines path with minimum state metric is used. The EPR-4 viterbi decoder is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology and consists of about 15,300 transistors and has 250 Mbps data rates under 3.3 volts.

본 논문에서는 자기 디스크 출력 채널에 사용되는 EPR-4 비터비 디코더 회로를 설계하였다. 비터비 디코더는 ACS 회로, 경로 메모리, 최소값 감지회로, 출력 선택 회로로 구성되었다. 설계한 EPR-4 비터비 디코더는 (1,7) RLL 코드를 사용하여 하드웨어 구현에 필요한 상태수를 8개에서 6개로 감소시켰으며, ACS 연산시 누적 동작과정에서 발생할 수 있는 오버플로우 문제를 처리하기 위해 2의 부소 연산에 바탕을 둔 modulo 비교를 사용하였다. 그리고 경로 메모리 회로에서 6개 출력이 수렴하지 않는 경우 최소 state metric 값을 경로에서 최종 결과값을 결정하도록 파이프라인 구조의 최소값 감지회로를 사용하였다. EPR-4 비터비 디코더 회로는 0.35 $\mu\textrm{m}$ CMOS 공정에 맞추어 설계되었으며, 트랜지스터 개수는 약 15,300 이며, 3.3V의 전압조건에서 최대 데이터 수신율은 250Mbps이다.

Keywords

References

  1. IEEE Trans., Magnetics. v.24 no.6 Partial Response Signalling in a Magnetic Recording Channel J.J. Moon;L.R. Carley
  2. IEEE Proceedings v.61 The Viterbi Algorithm G. D. Forney, Jr
  3. IBM Journal of Research and Development Application of Partial-Response Channel Coding to Magnetic Recording System H.Kobayashi;D.T. Tang
  4. IEEE J. on Selected Area Communication v.10 no.1 A PRML System for Digital Magnetic Recording R.D. Ciderciyan;F.Dolvio;R. Hermann;W. Hirt;W. Schoot
  5. IEEE Communication Magzine Adaptive Equalization in Magnetic-Disk Storage Channels John M. Cioffi
  6. Tech. Roport, IBM Research Report RZ 1177 Viterbi Detectors for Partial Response class IV Signaling : Theory and Implementation F. Dolvio;G. Ungerboeck
  7. IEEE CICC '1993 CMOS Implementation of A Viterbi Detector for Hard Disk Drives Pablo A. Ziperrovich;Jack K. Wolf
  8. Memorandum No UCB/ERL M93/72 Low Power High Speed DSP Architecture for Magnetic Disk PRML Read Channel See-Hoi Caesar Wong
  9. IEEE Trans. on Comm. v.34 no.5 Viterbi detection of class-IV partial response on a magnetic recording channel R.W. Wood;D.A. Petersen
  10. The Bell Systems Technical Journal Optimal Reception for Binary Partial Response Channels M.J. Ferguson
  11. IEEE Trans. on Magnetics v.27 no.6 A New Digital Signal Processing Channel for Data Storage Products Arvind M. Patel
  12. ICC '95 Simplified EPRML Methods based on Selective ACS for High Density Recording Channels Naoya Kobayashi;Wataru Sakurai;Seiichi Mita
  13. GLOBECOM '91 Dynamic Threshold Implementation of the Maximum-Likelihood Detector for the EPR-4 Channel Kelly J. Knudson;Jack K. Wolf;Laurence B. Milstein
  14. Journal of Korean Physics Society A High Speed VLSI Architecture of Adaptive Equalizer and Viterbi Decoder for EPR-IV Magnetic Disk Read Channel Byeoun-Yoon Choi;Bang-Sup Song
  15. ICC '1990 VLSI Architecture for Metric Normalization in the Viterbi Algorithm C. Bernald Shung;Gottfried Ungerboeck;Hemant K. Thapar;Paul Siegel
  16. IEEE Trans. on Communications v.37 no.11 An Alternative to Metric Rescaling in Viterbi Decoders A.P. Hekstra
  17. IEEE Trans. Comm v.42 no.6 On the Performance of Data Receivers with a Restricted Detection Delay J.M.Bergmans
  18. IEEE Journal of Solid-State Circuits v.33 no.3 Low Power Viterbi Decoder for CDMA Mobile Terminals Inyup Kang;Alan N. Wilson
  19. IEEE Trans. Communications v.COM-29 no.9 Memory Management in a Viterbi Decoder Charles M. Rader
  20. IEEE Communication Magzine v.29 Modulation and Coding for Information Storage P. Siegel;J. Wolf
  21. Digital Design with Verilog HDL Eliezer Sternheim
  22. HSPICE User's Manual v.1-4 Avante Inc.
  23. IEEE J. Solid State Circuit v.32 no.1 New Single Clock CMOS Latches and Flip flops with Improved Speed and Power Savings Jiren Yuan;Christer Svenson