• ETRI Journal
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• v.38 no.1
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• ETRI Journal
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• v.39 no.1
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• pp.62-68
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• 2017

In this paper, we present the design and characterization analysis of a cascode GaN field-effect transistor (FET) for switching power conversion systems. To enable normally-off operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancement-mode Si metal-oxide-semiconductor FET and a high-BV depletion-mode (D-mode) GaN FET. This paper demonstrates a normally-on D-mode GaN FET with high power density and high switching frequency, and presents a theoretical analysis of a hybrid cascode GaN FET design. A TO-254 packaged FET provides a drain current of 6.04 A at a drain voltage of 2 V, a BV of 520 V at a drain leakage current of $250{\mu}A$, and an on-resistance of $331m{\Omega}$. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications.

• Journal of IKEEE
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• v.26 no.4
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• pp.553-559
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• 2022

In this paper, RC snubber circuit design technology for oscillation suppression in half-bridge configuration of cascode gallium nitride (GaN) field effect transistors (FETs) is analyzed. A typical wide band-gap (WBG) device, cascode GaN FET, has excellent high-speed switching characteristics. However, due to such high-speed switching characteristics, a false turn-off problem is caused, and an RC snubber circuit is essential to suppress this. In this paper, the commonly used experimental-based RC snubber design technique and the RC snubber design technique using the root locus method are compared and analyzed. In the general method, continuous circuit changes are required until the oscillation suppression performance requirement is met based on experimental experience . However, in root locus method, the initial value can be set based on the non-oscillation R-C map. To compare the performance of the two aforementioned design methods, a simulation experiment and a switching experiment using an actual double pulse circuit are performed.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.4
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• pp.1-8
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• 1998

An MMIC single-balanced upconverting mixer for PCS application has been successfully developed using an MMIC process employed by 1 .mu. ion implanted GaAs MESFET and passive lumped elements consisting of spiral inductor, Si3N4 MIM capacitors and NiCr resistors. The configuration of the mixer presented in this paper is two balanced cascode FET mixers with common-source self-bias circuits for single power supply operation. The dimension of the fabricated circuit including two active baluns intermodulation characteristic with two-tone excitation are also measured, showing -28.17 dBc at IF power of -30 dBm.