• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.449-452
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• 1998

We have studied the oxidatio nrte of $Si_{1-x}Ge_{x}$ epitaxial layer grown by MBE(molecular beam epitaxy). Oxidation were performed at 700.deg. C, 800.deg. C, 900.deg. C, and 1000.deg. C. After the oxidation, the results of AES(auger electron spectroscopy) showed that Ge was completely rejected out of the oxide and pile up at $SiO_{2}/$Si_{1-x}Ge_{x}$ interface. It is shown that the presence of Ge at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface changes the dry oxidation rate. The dry oxidation rate was equal to that of pure Si regardless of Ge mole fraction at 700.deg. C and 800.deg.C, while it was decreased at both 900.deg. C and 1000.deg.C as the Ge mole fraction was increased. The ry oxidation rates were reduced for heavy Ge concentration, and large oxidation time. In the parabolic growth region of $Si_{1-x}Ge_{x}$ oxidation, The parabolic rate constant are decreased due to the presence of Ge-rich layer. After the longer oxidation at the 1000.deg.C, AES showed that Ge peak distribution at the $SiO_{2}$/$Si_{1-x}Ge_{x}$ interface reduced by interdiffusion of silicon and germanium.

• 한국재료학회지
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• 제10권4호
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• pp.276-281
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• 2000

Si(111) 표면을 NH$_3$분위기에서 실리콘질화물(SiNx)로 변형시킨 후 탄화규소(silicon carbide, SiC) 박막을 성장하였다. 질화시간이 증가함에 따라 SiC 박막 두께가 감소함을 관찰하였다. 또한 성장변수에 따라 SiC/Si 계면에서 결정결함인 틈새를 없앨 수 있었다. 100nm, 300nm, 500nm의 SiNx/Si 기판 위에 SiC 박막을 성장시켰다. 성장된 SiC 박막들은 모두 [111]면을 따라 성장되었고, SiC 결정들이 원주형 낟알로 성장되었다. SiC/SiNx 계면에서 void를 관찰할 수 없었다. 이러한 실험 결과는 SOI 구조의 산화규소를 SiNx로 대체함으로써 SiC 소자 제작에 응용될 수 있는 방향을 제시하고 있다.

• 한국전기전자재료학회논문지
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• 제15권7호
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• pp.559-563
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• 2002

A threshold voltage model of SiC N-channel MOSFETs for high-temperature and hard radiation environments has been developed and verified by comparing with experimental results. The proposed model includes the difference in the work functions, the surface potential, depletion charges and SiC/$SiO_2$acceptor-like interface state charges as a function of temperature. Simulations of the model shoved that interface slates were the most dominant factor for the threshold voltage decrease as the temperature increase. To verify the model, SiC N-chnnel MOSFETS were fabricated and threshold voltages as a function of temperature were measured and compared wish model simulations. From these comparisons, extracted density of interface slates was $4{\times}10^{12}\textrm{cm}^{-2}eV^{-1}$.

• 한국결정성장학회지
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• 제9권6호
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• pp.558-562
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• 1999

승화 성장법을 적용하여 성장된 6H-SiC 결정에 대하여, KSV 이론과 성장 계면에서의 미사면(vicinal plane)상의 step 성장 양상을 근거로 하여, 성장 계면에서의 물질 흡착의 거동과 결함의 생성간의 상호 관계를 고찰하고, micropipes와 내부 결함의 생성 원인을 논하였다. micropipe와 면결함등의 결함들은 ledge 혹은 kink에 침입된 불순물에 의하여 step 성장의 진행이 방해받는 부분에 형성되었다. 따라서, SiC 결정에서 이들 결함의 생성은 SiC 결정 성장 계면에 형성되는 결정학적 step 성장면과 분자 또는 원자들의 격자 이동에 관련이 있음을 알 수 있었다.

• 한국재료학회지
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• 제28권2호
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• pp.118-123
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• 2018

5 nm-thick $SiO_2$ layers formed by plasma-enhanced chemical vapor deposition (PECVD) are densified to improve the electrical and interface properties by using nitric acid oxidation of Si (NAOS) method at a low temperature of $121^{\circ}C$. The physical and electrical properties are clearly investigated according to NAOS times and post-metallization annealing (PMA) at $250^{\circ}C$ for 10 min in 5 vol% hydrogen atmosphere. The leakage current density is significantly decreased about three orders of magnitude from $3.110{\times}10^{-5}A/cm^2$ after NAOS 5 hours with PMA treatment, although the $SiO_2$ layers are not changed. These dramatically decreases of leakage current density are resulted from improvement of the interface properties. Concentration of suboxide species ($Si^{1+}$, $Si^{2+}$ and $Si^{3+}$) in $SiO_x$ transition layers as well as the interface state density ($D_{it}$) in $SiO_2/Si$ interface region are critically decreased about 1/3 and one order of magnitude, respectively. The decrease in leakage current density is attributed to improvement of interface properties though chemical method of NAOS with PMA treatment which can perform the oxidation and remove the OH species and dangling bond.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.343-347
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• 2004

High oxidation temperature of SiC shows a tendency of carbide formation at the interface which results in poor MOSFET transfer characteristics. Thus we developed oxidation processes in order to get low interface charge densities. N-type 6H-SiC MOS capacitors were fabricated by different oxidation processes: dry, wet, and dry­reoxidation. Gate oxidation and Ar anneal temperature was $1150^{\circ}C.$ Ar annealing was performed after gate oxidation for 30 minutes. Dry-reoxidation condition was $950^{\circ}C,$ H2O ambient for 2 hours. Gate oxide thickness of dry, wet and dry-reoxidation samples were 38.0 nm, 38.7 nm, 38.5 nm, respectively. Mo was adopted for gate electrode. To investigate quality of these gate oxide films, high frequency C- V measurement, gate oxide leakage current, and interface trapped charge densities (Dit) were measured. The interface trapped charge densities (Dit) measured by conductance method was about $4\times10^{10}[cm^{-1}eV^{-1}]$ for dry and wet oxidation, the lowest ever reported, and $1\times10^{11}[cm^{-1}eV^{-1}]$ for dry-reoxidation

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.65-65
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• 2009

High temperature silicon carbide Schottky diode was fabricated with Au deposited on poly 3C-SiC thin film grown on p-type Si(100) using atmospheric pressure chemical vapor deposition. The charge transport mechanism of the diode was studied in the temperature range of 300 K to 550 K. The forward and reverse bias currents of the diode increase strongly with temperature and diode shows a non-ideal behavior due to the series resistance and the interface states associated with 3C-SiC. The charge transport mechanism is a temperature activated process, in which, the electrons passes over of the low barriers and in turn, diode has a large ideality factor. The charge transport mechanism of the diode was analyzed by a Gaussian distribution of the Schottky barrier heights due to the Schottky barrier inhomogeneities at the metal-semiconductor interface and the mean barrier height and zero-bias standard deviation values for the diode was found to be 1.82 eV and $s_0$=0.233 V, respectively. The interface state density of the diode was determined using conductance-frequency and it was of order of $9.18{\times}10^{10}eV^{-1}cm^{-2}$.

• 한국복합재료학회:학술대회논문집
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• 한국복합재료학회 2000년도 춘계학술발표대회 논문집
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• pp.175-183
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• 2000

The internal residual stresses within the multilayered structure with shan interface induced by the difference in thermal expansion coefficient between the materials of adjacent layers often provide the source of failure such as delamination of interfaces and etc. Recent development of the multilayered structure with functionally graded interface would be the solution to prevent this kind of failure. However a systematic thermo-mechanical analysis is needed fur the customized structural design of multilayered structure. In this study, theoretical model for the thermo-mechanical analysis is developed for multilayered structures of the Al-$SiC_p$ functionally graded composite for electronic packaging. The evolution of curvature and internal stresses in response to temperature variations is presented for the different combinations of geometry. The resultant analytical solutions are used for the optimal design of the multilayered structures with functionally graded interface as well as with sharp interface.

• 한국전기전자재료학회논문지
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• 제16권8호
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• pp.700-704
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• 2003

This paper describes on characteristics of 2" 3C-SiC wafer bonding using PECVD (plasma enhanced chemical vapor deposition) oxide and HF (hydrofluoride acid) for SiCOI (SiC-on-Insulator) structures and MEMS (micro-electro-mechanical system) applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si (001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR (attenuated total reflection Fourier transformed infrared spectroscopy). The root-mean-square suface roughness of the oxidized SiC layers was measured by AFM (atomic force microscope). The strength of the bond was measured by tensile strength meter. The bonded interface was also analyzed by IR camera and SEM (scanning electron microscope), and there are no bubbles or cavities in the bonding interface. The bonding strength initially increases with increasing HF concentration and reaches the maximum value at 2.0 ％ and then decreases. These results indicate that the 3C-SiC wafer direct bonding technique will offers significant advantages in the harsh MEMS applications.ions.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.55-55
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.