• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Journal of the Korean Society of Industry Convergence
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• v.12 no.4
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• pp.215-219
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• 2009

A packaging technology based on flip-chip bonding and Pb-free solder for silicon pressure sensors on printed circuit board (PCB) is presented. First, the bump formation process was conducted by Pb-free solder. Ag-Sn-Cu solder and the pressed-screen printing method were used to fabricate solder bumps. The fabricated solder bumps had $189-223{\mu}m$ width, $120-160{\mu}m$ thickness, and 5.4-6.9 standard deviation. Also, shear tests was conducted to measure the bump shear strength by a Dage 2400 PC shear tester; the average shear strength was 74 g at 0.125 mm/s of test speed and $5{\mu}m$ shear height. Then, silicon pressure sensor packaging was implemented using the Pb-free solder and bump formation process. The characteristics of the pressure sensor were analogous to the results obtained when the pressure sensor dice are assembled and packaged using the standard wire-bonding technique.

• Journal of Drive and Control
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• v.13 no.2
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• pp.10-18
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• 2016

A front-end loader (FEL) mounted on an agricultural tractor is one of the most commonly used implements to mechanize routine agricultural tasks. When the FEL is used with a loaded bucket, careful operation is required to maintain safety and avoid spillage when the tractor passes a bump because a change in the gravity center of the tractor due to varied loadings can affect the stability of the tractor. Use of a boom suspension system consisting of accumulators and orifice dampers can be instrumental in reducing pitching vibrations while increasing the handling performance of the FEL-mounted tractor. The objective of this research was to reduce bump shocks by adding an orifice and a flow control valve to the original hydraulic circuit composed solely of accumulators. A simulation study was performed using the SimulationX program to investigate the effects of an accumulator and an orifice-throttle damper on bump shocks. Results showed that the peak pressure on a boom cylinder and the vertical acceleration of a bucket were significantly affected by use of both an accumulator and an orifice damper. In a field test conducted with a 75-kW tractor, the peak pressure of the boom cylinder, and the root mean square (RMS) vertical acceleration of the bucket and seat were reduced by on average, 23.0, 42.2, and 44.9% respectively, as compared to those measured with the original accumulator system, showing that an improved design for the accumulator hydraulic circuit can reduce bump shocks. Further studies are needed to design a tractor suspension system that includes the effects of cabin suspension and tires as well as dynamic analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.7-13
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• 2002

BSCT 320${\times}$240 IRFPA detector module is implemented, which is a key component in uncooled thermal imaging systems. The detector module consists of two parts, infrared sensitive pixel array and read-out integrated circuit(ROIC). The BSCT 320${\times}$240 pixels are made by laser scribe process and 10-${\mu}m$ micro-bump to satisfy 50-${\mu}m$ pitch and 95-% fill-factor. The ROIC has been designed to electrically address the pixels sequentailly and to improve signal-to-noise ratio with single transistor amplifier, HPF, tunable LPF and clamp circuit. The fabricated hybrid chip of detector and ROIC has been mounted on the TEC built-in ceramic package for more stable operation and tested for lots of electrical and optical properties. The IRFA sample has shown successful properties and met with good results of fill-factor, detectivity and responsivity.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.21-28
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• 2004

We have demonstrated the applicability of dry film photoresist (DFR) in photolithography process for fine pitch solder bumping on the polytetrafluoroethylene (PTFE/Teflon ) printed circuit board (PCB). The copper lines were formed with 100$\mu\textrm{m}$ width and 18$\mu\textrm{m}$ thickness on the PTFE test board, and varying the gaps between two copper lines in a range of 100-200$\mu\textrm{m}$. The DFRs of 15$\mu\textrm{m}$ thickness were laminated by hot roll laminator, by varying laminating temperature from $100{\circ}C$ to 15$0^{\circ}C$ and laminating speed from 0.28-0.98cm/s. We have found the optimum process of DFR lamination on PTFE PCB and accomplished the formation of indium solder bumps. The optimum lamination condition was temperature of $150^{\circ}C$ and speed of about 0.63cm/s. And the smallest size of indium solder bump was diameter of 50$\mu\textrm{m}$ with pitch of 100$\mu\textrm{m}$.

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.1
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• pp.24-29
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• 2006

A new oscillatory neural circuit with computational function has been designed and been designed and fabricated in an $0.5{\mu}m$ double poly CMOS technology. The proposed oscillatory circuit consists of 3 neural oscillators with excitatory synapses and a neural oscillator with inhibitory synapse. The oscillator block which is a basic element of the neural circuit is designed with a variable negative resistor and 2 transconductors. The variable negative resistor which is used as a input stage of the oscillator consist of a bump circuit with Gaussian-like I-V curve. SPICE simulations of a designed neural circuit demonstrate cooperative computation. Measurements of the fabricated neural chip in condition of ${\pm}$ 2.5 V power supply are shown and compared with the simulated results.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2006.11a
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• pp.185-188
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• 2006

생체 신경세포를 모방하는 진동성 신경 셀을 아날로그 집적회로로 설계한다. 진동성 신경셀은 입력신호 취합을 위한 취합회로와 신경 펄스 발생회로, 신경펄스 발생을 위한 범프회로와 트랜스콘덕터로 이루어지는 부성저항 블록으로 구성된다. $0.35{\mu}m$ 2중 폴리 공정 파라미터를 이용하여 SPICE 모의실험을 실시하여 입력 신호 유무 및 크기변화에 따른 출력 펄스의 발생을 얻어 진동성 신경회로의 가능성을 확인한다.

• Korean Journal of Materials Research
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• v.12 no.9
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• pp.750-760
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• 2002

In this study, three solders, Sn-37Pb, Sn-3.5Ag, and Sn-3.8Ag-0.7Cu were screen printed on both electroless Ni/Au and OSP metal finished micro-via PCBs (Printed Circuit Boards). The interfacial reaction between PCB metal pad finish materials and solder materials, and its effects on the solder bump joint mechanical reliability were investigated. The lead free solders formed a large amount of intermetallic compounds (IMC) than Sn-37Pb on both electroless Ni/Au and OSP (Organic Solderabilty Preservatives) finished PCBs during solder reflows because of the higher Sn content and higher reflow temperature. For OSP finish, scallop-like $Cu_{6}$ /$Sn_{5}$ and planar $Cu_3$Sn intermetallic compounds (IMC) were formed, and fracture occurred 100% within the solder regardless of reflow numbers and solder materials. Bump shear strength of lead free solders showed higher value than that of Sn-37Pb solder, because lead free solders are usually harder than eutectic Sn-37Pb solder. For Ni/Au finish, polygonal shaped $Ni_3$$Sn_4$ IMC and P-rich Ni layer were formed, and a brittle fracture at the Ni-Sn IMC layer or the interface between Ni-Sn intermetallic and P-rich Ni layer was observed after several reflows. Therefore, bump shear strength values of the Ni/Au finish are relatively lower than those of OSP finish. Especially, spalled IMCs at Sn-3.5Ag interface was observed after several reflow times. And, for the Sn-3.8Ag-0.7Cu solder case, the ternary Sn-Ni-Cu IMCs were observed. As a result, it was found that OSP finished PCB was a better choice for solders on PCB in terms of flip chip mechanical reliability.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.4
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• pp.275-281
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• 2003

A new neural oscillator has been designed and fabricated in an 0.5 ${\mu}{\textrm}{m}$ double poly CMOS technology. The proposed neural oscillator consists of a nonlinear variable resistor with negative resistance as well as simple transconductors and capacitors. The variable negative resistor which is used as a input stage of the oscillator consists of a positive feedback transconductors and a bump circuit with Gaussian-like I-V curve. The proposed neural oscillator has designed in integrated circuit with SPICE simulations. Simulations of a network of 4 oscillators which are connected with excitatory and inhibitory synapses demonstrate cooperative computation. Measurements of the fabricated oscillator chip with a $\pm$ 2.5 V power supply is shown and compared with the simulated results.

• Journal of Digital Convergence
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• v.14 no.5
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• pp.325-331
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• 2016

In driving at evening or night, we are not able to recognize the speed bump and so stop suddenly. It could result in accidents. And also, we have a restriction of street light installation in farm road because it could be harmful to the crops and driver could not recognize the walking people. It needs to develop the speed bump with light and streetlight to be non harmful to the crops. So, we develop both the speed bump and streetlight with LED which could be non harmful to the crops and be increased recognition of walking people in farm road. For LED lighting power, we use the solar cells, and piezoelectric elements. It has automatic on/off according to power saving rates without illumination sensor. Minimization of circuit elements and design of minimum resisters and low power LED was used for power saving in assuring 3-days.