• Title/Summary/Keyword: bottom gate

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Dependence of Conduction Path for Device Parameter of DGMOSFET Using Series (급수를 이용한 DGMOSFET에서 소자 파라미터에 대한 전도중심 의존성)

  • Han, Jihyung;Jung, Hakkee;Jeong, Dongsoo;Lee, Jongin;Kwon, Ohshin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.835-837
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    • 2012
  • In this paper, we have been analyzed conduction path by device parameter of double gate(DG) structure that have top gate and bottom gate. The Possion equation is used to analytical. The change of conduction path have been investigated for various channel lengths, channel thickness and gate oxide thickness using this model, given that these parameters are very important in design of DGMOSFET. The optimum channel doping concentration is determined as the deviation of conduction path is considered according to channel doping concentration.

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Analysis of Lattice Temperature in Super Junction Trench Gate Power MOSFET as Changing Degree of Trench Etching

  • Lee, Byeong-Il;Geum, Jong Min;Jung, Eun Sik;Kang, Ey Goo;Kim, Yong-Tae;Sung, Man Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.3
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    • pp.263-267
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    • 2014
  • Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don't have a great effect on temperature change.

Study on OTFT-Backplane for Electrophoretic Display Panel (전기영동 디스플레이 패널용 OTFT-하판 제작 연구)

  • Lee, Myung-Won;Ryu, Gi-Sung;Song, Chung-Kun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.7
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    • pp.1-8
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    • 2008
  • We fabricated flexible electrophoretic display(EPD) driven by organic thin film transistors(OTFTs) on plastic substrate. We designed the W/L of OTFT to be 15, considering EPD's transient characteristics. The OTFTs employed bottom contact structure and used Al for gate electrode, the cross-linked polyvinylphenol for gate insulator, pentacene for active layer. The plastic substrate was coated by PVP barrier layer in order to remove the islands which were formed after pre-shrinkage process and caused the electrical short between bottom scan and top data metal lines. Pentacene active layer was confined within the gate electrodes so that the off current was controlled and reduced by gate electrodes. Especially, PVA/Acryl double layers were inserted between EPD panel and OTFT-backplane in order to protect OTFT-backplane from the damages created by lamination process of EPD panel on the backplane and also accommodate pixel electrodes through via holes. From the OTFT-backplane the mobility was $0.21cm^2/V.s$, Ion/Ioff current ratio $10^5$. The OTFT-EPD panel worked successfully and demonstrated to display some patterns.

Salinity Changes and Bottom Water Particle Exchange Simulations in Response to Sluice Gate Operations at Saemangeum Lake (새만금 배수갑문 운영에 따른 염분 변화와 저층수의 입자교환 모의)

  • Seonghwa Park;Jonggu Kim;Minsun Kwon
    • Journal of the Korean Society of Marine Environment & Safety
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    • v.29 no.6
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    • pp.562-575
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    • 2023
  • In an effort to improve water quality, the South Korean government has implemented measures to increase seawater circulation in Saemangeum Lake. We analyzed the effect of increasing the frequency of seawater circulation based on salinity levels and bottom water exchange in the lake, using an environmental fluid dynamics code model. When the sluice gate opening and shutting frequency increased from once to twice per day, the internal water level of Saemangeum Lake increased by up to ~0.7 m. The salinity increased by 2.12 psu near the western breakwater and decreased by 1.18 psu near the freshwater inlet. We analyzed the extent of bottom water exchange using a particle tracing method and observed that the residual rate of particles shallower than 5 m in water depth decreased by 2.52% in Case 2 (opening and shutting twice per day) compared to Case 1 (opening and shutting once per day). This indicates that increasing the frequency of sluice gate opening and shutting would promote enhanced bottom water exchange. Consequently, the increased salinity and bottom water exchange associated with increased seawater circulation are expected to improve water quality in Saemangeum Lake.

Highly Reliable Trench Gate MOSFET using Hydrogen Annealing (수소 열처리를 이용한 고신뢰성 트렌치 게이트 MOSFET)

  • 김상기;노태문;박일용;이대우;양일석;구진근;김종대
    • Journal of the Korean Vacuum Society
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    • v.11 no.4
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    • pp.212-217
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    • 2002
  • A new technique for highly controllable trench corner rounding at the top and bottom of the trench using pull-back and hydrogen annealing has been developed and investigated. The pull-back process could control the trench corner rounding radius at the top comers of the trench. The silicon migration generated by hydrogen annealing at the trench coiners provided (111) and (311) crystal planes and gave a uniform gate-oxide thickness, resulting in high reliable trench DMOSFETs with highly breakdown voltages and low leakage currents. The breakdown voltage of a trench DMOSFET fabricated using hydrogen annealing was increased by 25% compared with a conventional DMOSFET. The reasonable drain current of 45.3 A was obtained when a gate voltage of 10 V was supplied. The on-resistance of the trench gate DMOSFET fabricated using the trench cell of 45,000 was about 55 m(at a gate voltage of 10 V under a drain current of 5 A.

The Estimation of Water Quality Changes in the Keum River Estuary by the Dyke Gate Operation Using Long-Term Data (장기관측자료에 의한 금강하구둑 수문조작에 따른 수질 변화 평가)

  • KWON Jung-No;KIM Jong-Gu;KO Tae-Seung
    • Korean Journal of Fisheries and Aquatic Sciences
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    • v.34 no.4
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    • pp.348-354
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    • 2001
  • This study was conducted to estimation of change characteristics for water quality by the dyke gate operation in the Keum River estuary. The estimation data made use of surveyed data in Keum River estuary by NERDI (National Fisheries Research and Development Institute) during $1990\~1999$. Shown to compare water quality changes at st. A and st. D in Figure 1, the concentrations of TSS, COD and nutrients at st. A were as high as about $2\~4$ times than those at st. D due to affection of fresh water discharge in the Keum River. The percentages of water quality change at surface water by dyke gate operation in the Keum River estuary were shown that TSS (Total Suspended Solid) was decrease to $56\%,\;47\%$ at st. A and D, and COD (Chemical Oxygen Demand) was increase to $68\%,\;71\%$ at st. A and D, respectively. The changes percentage of DIN (Dissolved Inorganic Nitrogen) by dyke gate operation in the Keum River estuary were increase high to $95\%$ at surface water and $7\sim30\%$ at bottom water, but those of DIP (Dissolved Inorganic Phosphorus) were increase to $2.8\sim8.6\%$ at surface water and $28\%$ at bottom water. The range of fluctuation for water quality at each station by dyke gate operation has shown that salinity and TSS are little better than before dyke gate operation, but COD show highly fluctuation. Also we studied estimation of characteristics of water quality change by the season, COD was increased except the summer, TSS was decreased to all season. DIN was increased to about $61\sim172.1\%$ for all season, but DIP was increased to the spring and decreased to the autumn, DIN enrichment in the estuary by dyke gate operation are interpreted to improvement of organic matter decomposition and nitrification by increasing the residence time and to increase nutrient flux in sediments due to decreasing dissolved oxygen and increasing a deposit matter.

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Improvement of Electrical Characteristics of Vertical NPT Trench Gate IGBT using Trench Emitter Electrode (트랜치 에미터 전극을 이용한 수직형 NPI 트랜치 게이트 IGBT의 전기적 특성 향상 연구)

  • Lee Jong-Seok;Kang Ey-Goo;Sung Man-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.10
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    • pp.912-917
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    • 2006
  • In this paper, Trench emitter electrode IGBT structure is proposed and studied numerically using the device simulator, MEDICI. The breakdown voltage, on-state voltage drop, latch up current density and turn-off time of the proposed structure are compared with those of the conventional trench gate IGBT(TIGBT) structures. Enhancement of the breakdown voltage by 19 % is obtained in the proposed structure due to dispersion of electric field at the edge of the bottom trench gate by trench emitter electrode. In addition, the on-state voltage drop and the latch up current density are improved by 25 %, 16 % respectively. However increase of turn-off time in proposed structures are negligible.

Effect of the Hydrophobicity of Hybrid Gate Dielectrics on a ZnO Thin Film Transistor

  • Choi, Woon-Seop;Kim, Se-Hyun
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.6
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    • pp.257-260
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    • 2010
  • Zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were prepared by the use of injector type atomic layer deposition. Two hybrid gate oxide systems of different polarity polymers with silicon oxide were examined with the aim of improving the properties of the transistors. The mobility and threshold voltage of a ZnO TFT with a poly(4-dimethylsilyl styrene) (Si-PS)/silicon oxide hybrid gate dielectric had values of 0.41 $cm^2/Vs$ and 24.4 V, and for polyimide/silicon oxide these values were 0.41 $cm^2/Vs$ and 24.4 V, respectively. The good hysteresis property was obtained with the dielectric of hydrophobicity. The solid output saturation behavior of ZnO TFTs was demonstrated with a $10^6$ on-off ratio.

The thickness effect on surface and electrical properties of PVP layer as insulator layer of OTFTs (OTFT 소자의 절연층으로써 두께에 따른 PVP 층의 표면 및 전기적 특성)

  • Seo, Choong-Seok;Park, Yong-Seob;Park, Jae-Wook;Kim, Hyung-Jin;Yun, Deok-Yong;Hong, Byung-You
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.245-245
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    • 2008
  • In this work, we describe the characterization of PVP films synthesized by spin-coater method and fabricate OTFTs of a bottom gate structure using pentacene as the active layer and polyvinylphenol (PVP) as the gate dielectric on Au gate electrode. We investigated the surface and electrical properties of PVP layer using an AFM method and MIM structure, and estimated the device properties of OTFTs including $I_D-V_D$, $I_D-V_G$, threshold voltage $V_T$, on/off ratio, and field effect mobility.

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Two-step electron beam lithography to fabricate 20 nm T-gate (20 nm급 T-형 게이트 제작을 위한 2단 전자 빔 노광 공정)

  • Lee, Kang-Sung;Kim, Young-Su;Lee, Kyung-Taek;Hong, Yun-Ki;Jeong, Yoon-Ha
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.555-556
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    • 2006
  • In this paper, we have proposed a novel process using two-step electron beam lithography to fabricate 20 nm T-gates for high performance MODFETs. Two-step lithography reduces electron forward scattering by defining the foot on a thin (100 nm) bottom-layer of polymethyl methacrylate (PMMA) at the second step, the T-gate head having been developed at the first step. Adopting a low temperature development technique for the second step reduces the detrimental effect of head exposure on foot definition. We have shown that 20 nm T-gate can be patterned with this process.

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