• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.180-184
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• 2013

In this paper, a low power antenna switch controller IC is designed using a silicon-on-insulator (SOI) CMOS technology. To improve power handling capability and harmonic distortion performance of the antenna switch, the proposed antenna switch controller provides 3-state logic level such as +VDD, GND, and -VDD for the gate and body of switch of FETs according to decoder signal. By employing input-coupled current ring oscillator and hardware efficient level shifter, the proposed controller greatly reduces power consumption and hardware complexity. It consumes 135 ${\mu}A$ at a 2.5 V supply voltage in active mode, and occupies $1.3mm{\times}0.5mm$ in area. In addition, it shows fast start-up time of 10 ${\mu}s$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.163-166
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• 2004

모바일향 90nm DRAM을 개발하기 위하여 비대칭 채널 구조를 갖는 Recess Channel Array Transistor (RCAT)로 cell transistor를 구현하였다. DRAM cell transistor에서 junction leakage current 증가는 DRAM retention time 열화에 심각한 영향을 미치는 요인으로 알려져 있으며, DRAM의 minimum feature size가 점점 감소함에 따라 short channel effect의 영향으로 junction leakage current는 더욱 더 증가하게 된다. 본 실험에서는 short channel effect의 영향에 의한 junction leakage current를 감소시키기 위하여 Recess Channel Array Transistor를 도입하였고, cell transistor의 채널 영역을 비대칭으로 형성하여 data retention time을 증가시켰다. 비대칭 채널 구조을 이용하여 Recess Channel Array Transistor를 구현한 결과, sub-threshold 특성과 문턱전압, Body effect, 그리고, GIDL 특성에는 큰 유의차가 보이지 않았고, I-V특성인 드레인 포화전류(IDS)는 대칭 채널 구조인 transistor 대비 24.8% 정도 증가하였다. 그리고, data retention time은 2배 정도 증가하였다. 본 실험에서 얻은 결과는 향후 저전압 DRAM 개발과 응용에 상당한 기여를 할 것으로 기대된다.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.1-9
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• 2010

This paper describes a ultrasonic signal processing front-end IC for distance range meter and body detector. The burst shaped ultrasonic signal is generated by a self oscillator and its frequency range is about 40[kHz]-300[kHz]. The generated ultrasonic signal transmit through piezo resonator. The another piezo device transduce from received ultrasonic signal to electrical signals. This front-end IC contained low noise amplifier, band pass filter, busrt detector and time pulse generator and so on. This IC has two type of new idea for improve function and performance, which are self frequency control (SFC) and Variable Gain Control amplifier (VGC) scheme. The dimensions and number of external parts are minimized in order to get a smaller hardware size. This device has been fabricated in a O.6[um] double poly, double metal 40[V] High Voltage CMOS process.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.7
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• pp.867-872
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• 2010

Unused energy derived from sources in nature can be captured and stored for future use, for example, to recharge a battery or power a device; this process of capturing and storing energy is called energy harvesting. Extensive investigations are being carried out in order to use piezoelectricity to harvest the energy generated by body movements or machine vibrations. This paper presents a simple analytical model that describes the output voltage effectiveness of a Piezocomposite Generating Element (PCGE) from vibration and its experimental verification. PCGE is composed of carbon/epoxy, PZT, and glass/epoxy layers. During the manufacturing process, the stacked layers were cured at $177^{\circ}C$ in an autoclave, which created residual stresses in PCGE and altered the piezoelectric properties of the PZT layer. In the experiments, three kinds of lay-up configurations of PCGE were considered to verify the proposed prediction model and to investigate its capability to convert oscillatory mechanical energy into electrical energy. The predicted performance results are in good agreement with observed experimental ones.

• Journal of Sensor Science and Technology
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• v.17 no.1
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• pp.1-8
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• 2008

Recently, capsule endoscope was developed to observe small intestine in human body. However, the capsule does not have any locomotive ability, which reduces the benefit of the capsule endoscope. Many researches have done to give locomotion to the capsule, still it consumes too much power to generate the motion by small battery. One of the moving method is electrical stimulus that consumes less power than many methods. The electrical stimulus method causes contraction in the small intestine, and it moves the capsule. Some of papers showed it is possible to guide the capsule by electrical stimulus, however the relationship between electrical stimulus at the mucous and contraction force in the small intestine is not reported, yet. In this paper, the mucous in the small intestine was stimulated, and measured the contraction force in the small intestine is shown. The result shows, the relationship between electrical stimulus parameters (voltage, duration) and contraction force. Also, equation between electrical stimulus parameters and contraction force is roughly induced.

• Korean Journal of Applied Biomechanics
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• v.25 no.3
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• pp.283-291
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• 2015

Objective : The purpose of this study was to determine the differences in the head and tibial acceleration signal magnitudes, and their powers and shock attenuations between flat-footed and normal-footed running. Methods : Ten flat-footed and ten normal-footed subjects ran barefoot on a treadmill with a force plate at 3.22m/s averaged from their preferred running speed using heel-toe running pattern while the head and tibial acceleration in the vertical axis data was collected. The accelerometers were sampled at 2000 Hz and voltage was set at 100 mv, respectively. The peak magnitudes of the head and tibial acceleration signals in time domain were calculated. The power spectral density(PSD) of each signal in the frequency domain was also calculated. In addition to that, shock attenuation was calculated by a transfer function of the head PSD relative to the tibia PSD. A one-way analysis of variance was used to determine the difference in time and frequency domain acceleration variables between the flat-footed and normal-footed groups running. Results : Peaks of the head and tibial acceleration signals were significantly greater during flat-footed group running than normal-footed group running(p<.05). PSDs of the tibial acceleration signal in the lower and higher frequency range were significantly greater during flat-footed running(p<.05), but PSDs of the head acceleration signal were not statistically different between the two groups. Flat-footed group running resulted in significantly greater shock attenuation for the higher frequency ranges compared with normal-footed group running(p<.05). Conclusion : The difference in impact shock magnitude and frequency content between flat-footed and normal-footed group during running suggested that the body had different ability to control impact shock from acceleration. It might be conjectured that flat-footed running was more vulnerable to potential injury than normal-footed running from an impact shock point of view.

• Journal of the Korean Ceramic Society
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• v.38 no.2
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• pp.143-151
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• 2001

Ca/LiCl-KCl/CaCrO$_4$열 전지계의 양극재료로서 BCT(Body-Centered Tetragonal) 결정구조를 갖는 CaCrO$_4$분말을 GNP로 합성하고, SEM, TEM, XRD를 이용하여 그 미세구조를 분석하였다. GNP 공정에 의한 CaCrO$_4$분말은 단일상으로 0.5$mu extrm{m}$ 이하의 입자 크기를 가지며 균일하게 분포한 반면, 기존의 분말 혼합법은 높은 하수 온도 및 장시간의 하소 조건을 필요하므로 미세한 분말 합성이 어렵고 pellet 형태로 만들었을 때 GNP 분말에 비해 비표면적이 현저하게 작기 때문에 전극 재료로써 유리하지 못하다. Ca/LiCl-KCl/CaCrO$_4$계의 전기 화학적인 특성을 평가해본 결과 전지셀을 Ca/DEB(LiCl-KCl+CaCrO$_4$+SiO$_2$)와 같은 DEB 형태로 만들었을 때 $600^{\circ}C$의 온도에서 2.0 V이상 (<100 mA/㎤)의 안정한 전압이 5분 이상 유지되었다. 그러나 3층 전극 셀(Ca/LiCl/KCl/ CaCrO$_4$)에서는 동일한 온도에서 2.0 V이상 (<100 mA/㎤)의 전압이 7분 이상 유지되었으나 불안정한 전압 변동 및 낮은 peak voltage로 인해 DEB 셀의 전지 특성이 더 우수한 것으로 생각된다. 양극 재료의 제조 방법의 관점에서 볼 때, 동일한 DEB(Depolarizer : Electrolyte : Binder=25 : 70 : 5 wt%) 조성의 셀 구성시, GNP 분말은 분말 혼합법에 의한 분말보다 반응 표면적이 훨씬 크기 때문에 GNP 양극 활 물질의 DEB 셀에서의 전지 수명이 더 길었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.22-29
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• 2006

We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as $5{\sim}6 times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage ($V_T$) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.1-6
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• 2010

A comparative analysis of quantum-mechanical and classical simulation regarding corner effect in a Saddle MOSFET has been carried out using a 3-D numerical simulator. The comparison has shown that quantum simulation gives correct description of device by providing accurate peak E-density position and magnitude at the Si-fin cross-section, hence accurate analysis of corner effect and its impact on device threshold voltage (Vth) characteristics is carried out. Moreover, rounding the Si-fin comers or lowering the body doping have been shown as two possible techniques to suppress the undesirable corner effect.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.197-199
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• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.