• Convergence Security Journal
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• v.22 no.4
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• pp.161-168
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• 2022

After the corona virus, as non-face-to-face services are activated, domain services that guarantee integrity by embedding sensing information of the Internet of Things (IoT) with block chain technology are expanding. For example, in areas such as safety and security using CCTV, a process is required to safely update firmware in real time and to confirm that there is no malicious intrusion. In the existing safe security processing procedures, in many cases, the person in charge performing official duties carried a USB device and directly updated the firmware. However, when private blockchain technology such as Hyperledger is used, the convenience and work efficiency of the Internet of Things environment can be expected to increase. This article describes scenarios in how to prevent vulnerabilities in the operating environment of various customers such as firmware updates and device changes in a non-face-to-face environment. In particular, we introduced the optimal blockchain technique for the Internet of Things (IoT), which is easily exposed to malicious security risks such as hacking and information leakage. In this article, we tried to present the necessity and implications of security management that guarantees integrity through operation applying block chain technology in the increasingly expanding Internet of Things environment. If this is used, it is expected to gain insight into how to apply the blockchain technique to guidelines for strengthening the security of the IoT environment in the future.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.708-714
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• 2000

In this paper, an one-dimensional VLSI array for high speed processing of fractal image compression algorithm based the quad-tree partitioning method is proposed. First of all, the single assignment code algorithm is derived from the sequential Fisher's algorithm, and then the data dependence graph(DG) is obtained. The two-dimension array is designed by projecting this DG along the optimal direction and the one-dimensional VLSI array is designed by transforming the obtained two-dimensional array. The number of Input/Output pins in the designed one-dimensional array can be reduced and the architecture of process elements(PEs) can he simplified by sharing the input pins of range and domain blocks and internal arithmetic units of PEs. Also, the utilization of PEs can be increased by reusing PEs for operations to the each block-size. For fractal image compression of 512X512gray-scale image, the proposed array can be processed fastly about 67 times more than sequential algorithm. The operations of the proposed one-dimensional VLSI array are verified by the computer simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.771-782
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• 2000

In this paper, an H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed as well as flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and a memory control part. The remaining portion of theH.263 video codec is implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an area-efficient architecture for the motion estimator of a multi-resolution block matching algorithm using multiple candidates and spatial correlation in motion vector fields (MRMCS), is suggested to reduce the chip size. Software optimization techniques are also explored by using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD)obtained from the motion estimator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.854-862
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• 1993

All of the CMOS analog and analog-digital systems have composed with several basic circuits, and among them, a important block, the amplifier part can affect the system's performance, Therefore, according to the uses in the system, the amplifier circuit have designed as various architectures (high-gain, low-noise, high-speed circuit, etc...). In this paper, we have proposed a new CMOS differential amplifier circuit. This circuit is differential to single ended input stage comprised of CMOS complementary gain circuits having internally biasing configurations. These architectures can be achieved the high gain and reduced the transistors for biasing. As a results of SPICE simulation with the standard $1.5{\mu}m$ processing parameter, the gain of the proposed circuit have a doubly value of the typical circuit's while maintaining other characteristics(phase margin, offset, etc...). And the proposed circuit is applicated in a simple CMOS comparator which has the settling time in 7nsec(CL=1pF) and the igh output swing $({\pm}4.5V)$.

• Journal of IKEEE
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• v.13 no.1
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• pp.1-10
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• 2009

Recently, some frequency domain CMA (Constant Modulus Algorithm) have been introduced in an effort to reduce computational complexities [1,2]. In [1], a fast algorithm that minimizing cost function designed for block input signal is employed, while in [2], a novel cost function that minimizing sample by sample input is used. Although, the two fast algorithm save computational complexities as compared to CMA, the convergence behaviors of the two fast algorithm show different results with repsect to CMA. Thus, in this paper, some analytical results on the error surface of the fast frequency domain CMA are introduced. From the analytical results, we show that the more recent algorithm [2] outperforms the previous algorithm [1]. Simulation results reveals that the recent algorithm [2] shows 50% enhanced convergence with respect to the old fast algorithm [1]. Also, we show that the recent fast algorithm [2] has comparable convergence performance with respect to conventional CMA algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7A
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• pp.762-769
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• 2007

Adaptive MIMO-OFDM (Orthogonal Frequency Division Multiplexing) system adaptively changes modulation scheme depending on feedback channel state information (CSI). The CSI feedback channel which is the reverse link channel has multiple symbol delays including propagation delay, processing delay, frame delay, etc. The unreliable CSI due to feedback delay degrades adaptive modulation system performance. This paper compares the MSE and data capacity with respect to delay and channel signal to noise ratio for the two multi-step channel prediction schemes, CTSBP and BTSBP, such that robust adaptive SISO-OFDM/MIMO-OFDM is designed over severe mobile multipath channel conditions. This paper presents an interpolation method to reduce feedback overhead for adaptive MIMO-OFDM and shows MSE with respect to interpolation interval.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1237-1245
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• 2006

This paper presented a hardware implementation of ARIA, which is a Korean standard l28-bit block cryptography algorithm. In this work, ARIA was designed technology-independently for application such as ASIC or core-based designs. ARIA algorithm was fitted in FPGA without additional components of hardware or software. It was confirmed that the rate of resource usage is about 19% in Altera EPXAl0F1020CI and the resulting design operates stably in a clock frequency of 36.35MHz, whose encryption/decryption rate was 310.3Mbps. Consequently, the proposed hardware implementation of ARIA is expected to have a lot of application fields which need high speed process such as electronic commerce, mobile communication, network security and the fields requiring lots of data storing where many users need processing large amount of data simultaneously.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1287-1294
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• 2006

In many current wireless packet data system, the short-burst transmissions are used, and training overhead is very significant for such short burst formats. So, the availability of the short training sequence and the fast converging algorithm is essential in the adaptive equalizer. In this paper, the new equalizer algorithm is proposed to improve the performance of a MTLMS (multiple-training least mean square) based DFE (decision feedback equalizer)using the short training sequence. In the proposed method, the output of the DFE is fed back to the LMS (least mean square) based adaptive DEF loop iteratively and used as an extended training sequence. Instead of the block operation using ML (maximum likelihood) estimator, the low-complexity adaptive LMS operation is used for overall processing. Simulation results show that the perfonnance of the proposed equalizer is improved with a linear computational increase as the iterations parameter in creases and can give the more robustness to the time-varying fading.

• Journal of Advanced Navigation Technology
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• v.11 no.4
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• pp.485-492
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• 2007

In this paper, we propose the receiver block error detection of the video codec and the image concealment algorithm using fuzzy inference. The proposed error detection and concealment algorithm gets SSD(Summation of Squared Difference) and BMC(Boundary Matching Coefficient) using the temporal and spatial similarity between corresponded blocks in the two successive frames. Proportional constant, ${\alpha}$, for threshold value, TH1 and TH2, is decided after fuzzy data is generated by each parameter. To examine the propriety of the proposed algorithm, random errors are inserted into the QCIF Susie standard image, then the error detection and concealment performance is simulated. To evaluate the efficiency of the algorithm, image quality is evaluated by PSNR for the error detection and concealed image by the existing VLC table and by the proposed method. In the experimental results, the error detection algorithm could detect all of the inserted error, the image quality is improved over 15dB after the error concealment compare to existing error detection algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.7
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• pp.4516-4521
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• 2014

Digital watermarking for digital image authentication and integrity schemes are based on fragile watermarking and can detect any modifications in a watermark embedded image by comparing the embedded watermark with the regenerated watermark. Therefore, the digital watermark for image authentication and integrity should be erased easily when the image is changed by digital image processing, such as scaling or filtering etc. This paper proposes an effective tamper detection scheme for digital images. In the proposed scheme, the original image was divided into many non-overlapping $2{\times}2$ blocks. The digital watermark was divided into two LSB of each block and the image distortion was imperceptible to the human eye. The watermark extraction process can be used to determine if the watermarked image has been tampered. The experimental results successfully revealed the effectiveness of the proposed scheme.