• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.309-312
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• 2002

Ferroelectric $Sr_{0.3}Ba_{0.7}Nb_{2}O_{6}$ (SBN30) thin films were deposited on Pt/Ti/$SiO_{2}$/Si(100) substrates by ion beam sputtering. During annealing treatment at $750^{\circ}C$, poling was attempted by applying dc voltage bias across polished surfaces. Phase relation, microstructure and crystallization behavior were examined using XRD and FE-SEM. Ferroelectric hysteresis characteristics were also determined where both remanent polarization and coercive values decreased with the increase of bias voltage. The measured remanent polarization and coercive field values at 5 V and 10 V bias were $36{\mu}C/cm^2$, $10{\mu}C/cm^2$ and 100kV /cm, 80kV /cm, respectively.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.22-28
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• 1998

A new type of FET source mixer with a single bias voltage has been presented. It is designed to operate at Vds=0 [V] with only one positive supply voltage, which makes mixer circuits simple. The proposed mixer has shown improved stability and less sensitivity to both bias and LO power compared with conventional active mixers. It also shows lower conversion loss than that of diode mixers. The minimum conversion loss measured at RF frequency of 5.6㎓ is 0.6㏈ for a LO frequency of 5.8㎓.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.257-260
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• 2007

Hydrogenated amorphous silicon thin film transistors were fabricated on a flexible metal substrate. A negative voltage at a floated gate can be induced by a negative substrate bias through a capacitor between the substrate and gate electrode. This can recover the shifted-threshold voltage to an original value.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.324-327
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• 2000

In this paper, the effects of negative and positive bias stress on p-channel poly-Si TFT's fabricated by excimer laser annealing have been investigated After positive and negative bias stress, transcon-ductance(g$_{m}$) is increased because of a reduction of the effective channel length due to the injected electron in the gate oxide. In the positive bias stress, the injection of hole is appeared after stress time of 3600sec and g$_{m}$ is decreased. On the other hand, the gate voltage at the maximum g$_{m}$, S-swing and threshold voltage(V$_{th}$) are decreased because of the interface state generation due to the injection of electrons into the gate oxide.e.ide.e.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.206-208
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• 1996

Thin films of magnesium oxide(MgO) were deposited on glass substrates by RF magnetron sputtering method. The characteristics of MgO thin films were analyzed as a function of various deposition conditions such as substrate temperature, substrate self-bias, input power and pressure. As the substrate temperature and bias voltage were increased, the grain size of MgO thin film increased. XRD peaks of (111) and (222) direction became dominant, as the substrate bias voltage increases and temperature decreases.

• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.88-93
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• 2020

Based on the capture-emission energy (CEE) maps of CMOS devices, a physics-informed machine learning model for the bias temperature instability (BTI)-induced threshold voltage shifts and low frequency noise is presented. In order to incorporate physics theories into the machine learning model, the integration of artificial neural network (IANN) is employed for the computation of the threshold voltage shifts and low frequency noise. The model combines the computational efficiency of IANN with the optimal estimation of Gaussian mixture model (GMM) with soft clustering. It enables full lifetime prediction of BTI under various stress and recovery conditions and provides accurate prediction of the dynamic behavior of the original measured data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1477-1483
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• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.9
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• pp.45-51
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• 2014

This work carried out for the effective synthesis characteristics of graphene nanowall film by controlling the electric field in a RF plasma CVD process. For that, the bipolar bias voltage was applied to the substrate such as Si and glass materials for the best chemical reaction of positive and negative charges existing in the plasma. For supplying the seed formation sites on substrate and removing the oxidation layer on the substrate surface, the electron bombardment into substrates was performed by a positive few voltage in hydrogen plasma. After that, hydrocarbon film, which is not a graphene nanowall, was deposited on substrates under a negative bias voltage with hydrogen and methane gases. At this step, the film on substrates could not easily identify due to its transparent characteristics. However, the transparent film was easily changed into graphene nanowall by the final hydrogen plasma treatment process. The resultant raman spectra shows the existence of significant large 2D peaks corresponding to the graphene.

• Journal of the Korean Vacuum Society
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• v.8 no.4B
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• pp.541-547
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• 1999

Reactive ion etching process for InP using BCl3/O2/Ar high density inductively coupled plasma was investigated. The experimental design method proposed by the Taguchi was utilized to cover the whole parameter range while maintaining reasonable number of actual experiments. Results showed that the ICP power and the chamber pressure were the two dominant parameters affectsing etch results. It was also observed that the etch rate decreased and the surface roughness improved as the ICP power and the bias voltage increased and as the chamber pressure decreased. The Addition of oxygen to the gas mixture drastically improved surface roughness by suppressing the formation of the surface reaction product. The optimum condition was ICP power 600W, bias voltage -100V, 10% $O_2$, 6mTorr, and $180^{\circ}C$, resulting in about 0.15$\mu\textrm{m}$ etch rate with smooth surfaces and vertical mesa sidewalls Also, the maximum etch rate of abut 4.5 $\mu\textrm{m}$/min was obtained at the condition of ICP power 800W, bias voltage -150V, 15% $O_2$, 8mTorr and $160^{\circ}C$.