• Transactions on Electrical and Electronic Materials
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• v.6 no.2
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• pp.57-62
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• 2005

Using intense pulsed ion beam evaporation technique, we have succeeded in the preparation of poly crystalline silicon thin films without impurities on silicon substrate. Good crystallinity and high deposition rate have been achieved without heating the substrate by using lEE. The crystallinity of poly-Si film has been improved with the high density of the ablation plasma. The intense diffraction peaks of poly-Si thin films could be obtained by using the substrate bias system. The crystallinity and the deposition rate of poly-Si thin films were increased by applying (-) bias voltage for the substrate.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.180-186
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• 2023

Positive bias temperature instability (PBTI) degradation of n⁺ and p⁺ poly-Si gate high-voltage(HV) SiO2 dielectric nMOSFETs was investigated. Unlike the expectation that degradation of n⁺/nMOSFET will be greater than p⁺/nMOSFET owing to the oxide electric field caused by the gate material difference, the magnitude of the PBTI degradation was greater for the p⁺/nMOSFET than for the n⁺/nMOSFET. To analyze the cause, the interface state and oxide charge were extracted for each case, respectively. Also, the carrier injection and trapping mechanism were analyzed using the carrier separation method. As a result, it has been verified that hole injection and trapping by the p⁺ poly-Si gate accelerates the degradation of p⁺/nMOSFET. The carrier injection and trapping processes of the n⁺ and p⁺ poly-Si gate high-voltage nMOSFETs in PBTI are detailed in this paper.

• Current Optics and Photonics
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• v.5 no.2
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• pp.173-179
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• 2021

The electroluminescence (EL) intensities of GaN-based light-emitting diodes (LEDs) are estimated based on their photoluminescence (PL) properties. The PL intensity obtained under open-circuit conditions is divided into two parts: the PL intensity under a forward bias lower than the optical turn-on voltage, and the difference between the PL intensities under open-circuit conditions and under forward bias. The luminescence induced by photoexcitation under a constant forward bias lower than the optical turn-on voltage is primarily the PL from the excited area of the LED. In contrast the intensity difference, obtained by subtracting the PL intensity under the forward bias from that under open-circuit conditions, contains the EL induced by the photocarriers generated during photoexcitation. In addition, a reverse photocurrent is generated during photoexcitation under constant forward bias across the LED, and can be correlated with the PL-intensity difference. The relationship between the photocurrent and PL-intensity difference matches well the relationship between the injection current and EL intensity of LEDs. The ratio between the photocurrent generated under a bias and the short-circuit current is related to the ratio between the PL-intensity difference and the PL intensity under open-circuit conditions. A relational expression consisting of the ratios, short-circuit current, and PL under open-circuit conditions is proposed to estimate the EL intensity.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 1999.10a
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• pp.73-75
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• 1999

• Proceedings of the Materials Research Society of Korea Conference
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• 1994.05a
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• pp.102-103
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• 1994

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1185-1188
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• 2007

The address discharge characteristics by the various scan-low and common-bias voltages are investigated based on measured address discharge time lags and $V_t$ close-curve analysis. The scan-low voltages are changed under the same voltage difference between the X and Y electrodes during an address period. As the voltage difference between the scan and address electrodes is increased during an address period, the address discharge time lag is shortened but the background luminance is increased. It is found that the improved address discharge characteristics is caused by the effect of the higher external applied voltage during an address period than the accumulated wall charges during a reset period and the high background luminance can be prevented by applying an address-bias voltage during a rising-ramp period and low reset voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.87-91
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• 1998

In this paper, We analyzed the current-voltage characteristics with n-type silicon substrates concentration and temperature variations (Room temperature, 50$^{\circ}C$, 75$^{\circ}C$) in platinum silicide and silicon junction. The electrical parameters of measurement are turn-on voltage, saturation current, ideality factor, barrier height, dynamic resistance in forward bias and reverse breakdown voltage according to variations of junction concentration of substrates and measurement temperature variations. As a result, the forward turn-on voltage, reverse breakdown voltage, barrier height and dynamic resistance were decreased but saturation currents and ideality factor were increased by substrates increased concentration variations in platinum silicide and n-silicon junction. In increased measurement temperature (RT, 50$^{\circ}C$, 75$^{\circ}C$), the extracted electrical parameter values of characteristics were rises by increased temperature variations according to the forward and reverse bias.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.41-47
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• 1998

We propose a new high speed and low power SOI inverter with dynamic threshold voltage that can operate with efficient body-bias control and free supply voltage. The performance of the proposed circuit is evaluated by both the BSIM3SOI circuit simulator and the ATLAS device simulator, and then compared with other reported SOI circuits. The proposed circuit is shown to have excellent characteristics. At the supply voltage of 1.5V, the proposed circuit operates 27% faster than the conventional SOI circuit with the same power dissipation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.83-88
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• 2003

The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with $492(H){\;}{\times}{\;}510(V)$ pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.