• 제목/요약/키워드: bandgap reference

검색결과 51건 처리시간 0.027초

CMOS 공정을 이용하는 동작온도에 무관한 펄스폭 변조회로 설계 (Design of Temperature Stable Pulse Width Modulation Circuit Using CMOS Process Technology)

  • 김도우;최진호
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 추계학술대회 논문집
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    • pp.186-187
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    • 2007
  • In this work, a temperature stable PWM(Pulse width modulation) circuit is proposed. The designed PWM circuit has a temperature dependent current source and a temperature independent voltage to compensate electrical characteristics with operating temperature. The variation of driving current is from about 4% to -6% in the temperature range $0^{\circ}C\;to\;70^{\circ}C$ compared to the current at the room temperature. The variation of bandgap voltage reference is from about 1.3% to -0.2% with temperature when the supply voltage is 3.3 volts. From simulation results, the variation of output pulse width is less than from 0.86% to -0.38% in the temperature range $0^{\circ}C\;to\;70^{\circ}C$.

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Analysis on Transition between Index- and Bandgap-guided Modes in Photonic Crystal Fiber

  • Hong, Kee Suk;Lim, Sun Do;Park, Hee Su;Kim, Seung Kwan
    • Journal of the Optical Society of Korea
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    • 제20권6호
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    • pp.733-738
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    • 2016
  • We calculate optical properties of guided modes of a hybrid-guiding photonic crystal fiber. The design and modeling of such hybrid-guiding PCF is made by replacing air holes with inserts of high refractive index material layer by layer in order. The optical properties such as mode intensity profile, mode dispersion, optical birefringence, confinement loss, and chromatic dispersion during transition of the guiding mechanism are analyzed and discussed. The guided modes in the hybrid-guiding region are also compared with those of reference index-guiding and bandgap-guiding photonic crystal fibers.

저전압 SoC용 밴드갭 기준 전압 발생기 회로 설계 (A Bandgap Reference Voltage Generator Design for Low Voltage SoC)

  • 이태영;이재형;김종희;심외용;김태훈;박무훈;하판봉;김영희
    • 한국정보통신학회논문지
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    • 제12권1호
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    • pp.137-142
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    • 2008
  • 본 논문에서는 $Low-V_T$ 트랜지스터가 필요 없는 로직공정으로 Parasitic NPN BJT를 이용하여 저 전압에서 동작 가능한 밴드갭 기준전압 발생기 회로를 제안하였다. $0.18{\mu}m$ triple-well 공정을 사용한 BGR회로를 측정 한 결과 VREF의 평균전압은 0.72V $3{\sigma}$는 45.69mV로 양호하게 측정되었다.

CMOS Bandgap 기준 전압/전류 발생기 및 방사능 응답 (A CMOS Bandgap Reference Voltage/Current Bias Generator And Its Responses for Temperature and Radiation)

  • 임규호;유성한;허진석;김광현;전성채;허영;김영희;조규성
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.1093-1096
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    • 2003
  • 본 논문에서는, CMOS APS Image Sensor 내에 포함되어 회로의 면적을 줄인 새롭게 제안된 CMOS Bandgap Reference Bias Generator (BGR)를 온도 및 방사능에 대한 응답을 실험하였다. 제안된 BGR 회로의 설계 목표는 V/sub DD/는 2.5V이상이고, V/sub ref/는 0.75V ± 0.5mV 마진을 가지게 하는 것이다. 제안된 BGR회로는 Level Shifter를 갖는 Differential OP-amp단과 Feedback-Loop를 가지는 Cascode Current Mirror를 사용하여 저전압에서도 동작을 가능하게 하였으며, 높은 출력저항 특성을 가지도록 하였다. 제안된 BGR회로는 하이닉스 0.18㎛ ( triple well two-poly five-metal ) CMOS 공정을 이용하여 Test Chip을 제작하였다. 온도의 변화와 Co-60 노출조건 하에서 Total ionization dose (TID) effect된 BGR회로의 V/sub ref/를 측정하여, 이를 평가하였다. 온도에 대한 반응은, 25℃ 일 때의 V/sub ref/에 대해, 각각 45 ℃에서 0.128%. 70℃에서 0.768% 변화하였다. 그리고 온도가 25℃일 때 50krad와 100krad의 방사능을 조사 하였을 경우, V/sub ref/는 각각 2.466%, 그리고 4.612% 변화하였다.

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A Clock and Data Recovery Circuit with Adaptive Loop Bandwidth Calibration and Idle Power Saved Frequency Acquisition

  • Lee, Won-Young;Jung, Chae Young;Cho, Ara
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권4호
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    • pp.568-576
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    • 2017
  • This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

A 70 MHz Temperature-Compensated On-Chip CMOS Relaxation Oscillator for Mobile Display Driver ICs

  • Chung, Kyunghoon;Hong, Seong-Kwan;Kwon, Oh-Kyong
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권6호
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    • pp.728-735
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    • 2016
  • A 70 MHz temperature-compensated on-chip CMOS relaxation oscillator for mobile display driver ICs is proposed to reduce frequency variations. The proposed oscillator compensates for frequency variation with respect to temperature by adjusting the bias currents to control the change in delay of comparators with temperature. A bandgap reference (BGR) is used to stabilize the bias currents with respect to temperature and supply voltages. Additional temperature compensation for the generated frequency is achieved by optimizing the resistance in the BGR after measuring the output frequency. In addition, a trimming circuit is implemented to reduce frequency variation with respect to process. The proposed relaxation oscillator is fabricated using 45 nm CMOS technology and occupies an active area of $0.15mm^2$. The measured frequency variations with respect to temperature and supply voltages are as follows: (i) ${\pm}0.23%$ for changes in temperature from -30 to $75^{\circ}C$, (ii) ${\pm}0.14%$ for changes in $V_{DD1}$ from 2.2 to 2.8 V, and (iii) ${\pm}1.88%$ for changes in $V_{DD2}$ from 1.05 to 1.15 V.

저전압용 CMOS 온-칩 기준 전압 및 전류 회로 (CMOS on-chip voltage and current reference circuits for low-voltage applications)

  • 김민정;이승훈
    • 전자공학회논문지C
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    • 제34C권4호
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    • pp.1-15
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    • 1997
  • This paper proposes CMOS on-chip voltage and current reference circuits that operate at supply voltages between 2.5V and 5.5V without using a vonventional bandgap voltage structure. The proposed reference circuits based on enhancement-type MOS transistors show low cost, compatibility with other on-chip MOS circuits, low-power consumption, and small-chip size. The prototype was implemented in a 0.6 um n-well single-poly double-metal CMOS process and occupies an active die area of $710 um \times 190 um$. The proposed voltage reference realizes a mean value of 0.97 V with a standard deviation of $\pm0.39 mV$, and a temperature coefficient of $8.2 ppm/^{\circ}C$ over an extended temeprature range from TEX>$-25^{\circ}C$ to $75^{\circ}C$. A measured PSRR (power supply rejection ratio) is about -67 dB at 50kHz.

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광송신기용 광파워 안정화 회로의 집적회로 설계 (Intergrated circuit design of power-stabilizing circuitry for optical transmitter)

  • 이성철;박기현;정행근
    • 전자공학회논문지B
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    • 제33B권3호
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    • pp.47-55
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    • 1996
  • An optical transmitter, which is a key component of the optical transmission system, converts the electrical signal to optical signal and consists of a high-speed current-pulse driver for laser diode and low-speed feedback loops that stabilize optical power against aging, power supply voltage fluctuations, and ambient temperature changes. In this paper, the power-stabilizing part, which forms the bulk of the optical transmitter circuitry was designed in integrted circuits. Operational amplifiers and reference voltage generation circuits, which were identified as key building blocks for the power-stabilizing feedback loops, were designed and were subsequently verified through HSPICE simulations. The designed operational amplifier consists of a two-stage folded cascode amplifier and class AB output stage, whereas the reference voltage is obtained by bandgap reference circuits. Finally the power-stabilizing circuitry was laid out based on 3\mu$m CMOS design rules for fabrication.

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MEMS 가속도센서를 위한 CMOS 인터페이스 회로 (CMOS Interface Circuit for MEMS Acceleration Sensor)

  • 정재환;김지용;장정은;신희찬;유종근
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2012년도 추계학술대회
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    • pp.221-224
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    • 2012
  • 본 논문에서는 MEMS 가속도센서를 위한 CMOS 인터페이스 회로를 설계하였다. 설계된 CMOS 인터페이스 회로는 CVC(Capacitance to Voltage Converter), 그리고 SC-Integrator와 Comparator를 포함하는 ${\Sigma}{\Delta}$ Modulator로 구성되어 있다. 회로에 일정한 Bias를 공급할 수 있도록 Bandgap Reference를 이용하였으며, 저주파 잡음과 offset을 감소시키기 위하여 ${\Sigma}{\Delta}$ Modulator에 CHS(Chopper-Stabilization) 기법을 사용하였다. 그 결과 설계된 ${\Sigma}{\Delta}$ Modulator의 출력은 입력 전압 진폭이 100mV가 증가할 때 duty cycle은 10%의 비율로 증가하고, 전체 회로의 Sensitivity는 x, y축은 0.45V/g, z축은 0.28V/g의 결과를 얻을 수 있었다. 제안된 CMOS 인터페이스 회로는 CMOS 0.35um공정을 이용하여 설계되었다. 입력 전압은 3.3V이며, 샘플링 주파수는 2MHz이다. 설계된 칩의 크기는 PAD를 포함하여 $0.96mm{\times}0.85mm$이다.

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Edge perturbation on electronic properties of boron nitride nanoribbons

  • K.L. Wong;K.W. Lai;M.W. Chuan;Y. Wong;A. Hamzah;S. Rusli;N.E. Alias;S. Mohamed Sultan;C.S. Lim;M.L.P. Tan
    • Advances in nano research
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    • 제15권5호
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    • pp.385-399
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    • 2023
  • Hexagonal boron nitride (h-BN), commonly referred to as Boron Nitride Nanoribbons (BNNRs), is an electrical insulator characterized by high thermal stability and a wide bandgap semiconductor property. This study delves into the electronic properties of two BNNR configurations: Armchair BNNRs (ABNNRs) and Zigzag BNNRs (ZBNNRs). Utilizing the nearest-neighbour tight-binding approach and numerical methods, the electronic properties of BNNRs were simulated. A simplifying assumption, the Hamiltonian matrix is used to compute the electronic properties by considering the self-interaction energy of a unit cell and the interaction energy between the unit cells. The edge perturbation is applied to the selected atoms of ABNNRs and ZBNNRs to simulate the electronic properties changes. This simulation work is done by generating a custom script using numerical computational methods in MATLAB software. When benchmarked against a reference study, our results aligned closely in terms of band structure and bandgap energy for ABNNRs. However, variations were observed in the peak values of the continuous curves for the local density of states. This discrepancy can be attributed to the use of numerical methods in our study, in contrast to the semi-analytical approach adopted in the reference work.