• Journal of Institute of Control, Robotics and Systems
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• v.10 no.2
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• pp.197-203
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• 2004

A real-time network in a distributed control system plays an important role for the reliable data transmission. Compared to the field-buses used in the past, TCP/IP protocol on the top of Ethered provides a compatibility between applications as well as an economical method to develop softwares. This paper proposes a modified TCP/IP structure for IEEE-1394 network, with which asynchronous and isochronous data transmission is selectively used for the real-time data transmission in a distributed control system. This paper also shows the performance of the proposed protocol by experiments.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.69-72
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• 1999

In this paper, the implementation method for the extending real-time execution in MMS Implementation is proposed. For this, the method of MMS over ATM(Asynchronous Transfer Mode) and IEEE 802.12 network is analyzed. By the analysis of service response time, making the ASIC of encoding and decoding parts are proposed for one of the real time extension in MMS. The main goals of this paper to analyze and propose suitable methods to meet the real time requirements in MMS applied system.

• Journal of KIISE:Databases
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• v.31 no.5
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• pp.457-467
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• 2004

The efficiency of algorithms managing data caches has a major impact on the performance of systems that utilize client-side data caching. In these systems, two versions of data can be maintained without an additional space overhead of the server by exploiting the replication of data in the server's buffer and clients' caches. In this paper, we present a new cache consistency algorithm employing versions: Two Versions-Callback Locking (2V-CBL). Our experimental results indicate that 2V-CBL provides good performance, particularly outperforms a leading cache consistency algorithm, Asynchronous Avoidance-based Gache Consistency, when some clients run only read-only transactions.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.17-26
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• 1999

In this paper, Bit selectable and Bi-directional Interface Device is described, which can communicate data with the peripheral devices. Specially, an algorithm of truth-table comparison that synthesizes the pulse-type sequential circuit pulse has been proposed to design the Interrupt Generator, and implemented in designing the Interrupt Register. Also, a description of the asynchronous design method is given to remove the clock skew phenomenon, and the output asynchronous control method which finds the optimal clock and controls all the enable signal of the output pins at the same time is presented. Using this technique interface ports have delay time of less-than 0.7ns.

• The Transactions of the Korea Information Processing Society
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• v.7 no.12
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• pp.3785-3793
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• 2000

Effective synchronization specification model which can specify temrxlral relationship among media resolving asynchronous problem due to variable network delay is necessary in a distributed multimedia system. Therefore in this paper, we propose RTPN(Real- Time Petri Net) synchronization specification model based on Petri Net for multimedia application in a distributed real time environment. The proposed RTPN model supplies a tlexible decsription of the temporal relationship among various media objects by defining primary key media and relative key media according to delay and importance among media. Firing rule is instantly executed by firing function based on QoS values which supports intra-media and inter-media syncbronization. And asynchronous control algorithm for resynchronization of presentation level is possible more effective supporting of QoS.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.384-387
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• 1999

In this paper, we have proposed a testing methodology for Speed-Independent asynchronous control circuits using the self-checking property where the circuit detects certain classes of faults during normal operation. To exploit self-checking properties of Speed-Independent circuits, the Proposed methodology generates tests from the specification of the target circuit which describes the behavior of the circuit. The generated tests are applied to a fault-free and a faulty circuit, and target faults can be detected by the comparison of the outputs of the both circuits. For the purpose of efficient comparison, reachability information of the both circuits in the form of BDD's is used and operations are conducted by BDD manipulations. The identification for undetectable faults in testing is also used to increase efficiency of the proposed methodology. The proposed identification uses only topological information of the target circuit and reachability information of the good circuit which was generated in the course of preprocess. Experimental results show that high fault coverage is obtained for synthesized Speed-Independent circuits and the use of the identification process decreases the number of tests and execution time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1171-1177
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• 2002

In this paper, we proposed a high speed IP(Internet Protocol) packet forwarding engine of ATM(Asynchronous Transfer Mode) based label edge routers for POS(Packet over SONET) interface. The forwarding engine uses TCAM(Ternary Content Addressable Memory) for high performance lookup processing of the packet received from POS interface. We have accomplished high speed IP packet forwarding in hardware by implementing the functions of high speed IP header Processing and lookup control into FPGA(Field Programmable Gate Array). The proposed forwarding engine has the functions of label edge routers as the lookup controller supports MPLS(Multiprotocol Label Switching) packet processing functionality.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.7
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• pp.356-371
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• 2001

본 논문에서는 비동기식 상위수준합성기 제작의 일환으로 효율적인 비동기식 제어부의 자동생성에 관한 방법을 제안한다. 제안된 방법은 목적시스템의 사양으로써 주어진 제어데이터흐름그래프로부터 일련의 체계적인 변환과정을 통하여, 제어부를 구성할 제어회로들에 대응하는 계층적으로 분할된 비동기식 유한상태기들의 집합을 유도한다. 유도된 비동기식 유한상태기들은 현존하는 비동기식 제어회로 합성기를 통하여 해저드 없는 비동기식 제어회로들로 합성되며, 이들은 상호간에 4단계 핸드셰이킹에 기반한 신호교환을 통하여 동작하면서 전체 시스템을 제어하는 계층적으로 분할된 비동기식 제어부를 구성한다. 획득한 제어부는 계층.분산적이며, 면적, 성능 및 합성시간의 측면에서 기존방식을 통하여 생성한 제어부에 비해 우월하다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3B
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• pp.487-492
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• 2000

The ABR(available bit rate) service has been developed to support data application over ATM(asynchronous Transfer mode) networks, and TCP is the most widely used transport layer protocol in existing data networks. Thus, the performance improvement of TCP over ABR is an issue of cardinal importance. In this paper, we propose algorithm of the adjustment of congestion window size utilizing RM(resource Management) cell information. The motivation is to use more reliable information in ER(explicit rate) field within RM cell to determine TCP window size. Simulations are performance using the suggested algorithm is improved, as compared to TCP-reno.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.2
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• pp.71-77
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• 2019

This study proposes a circulating current reduction method that uses high-frequency voltage compensation when carrier phase difference occurs between two inverters in MSIS. In MSIS, inverters are configured in parallel to increase power capacity and to increase efficiency by using inverters only as needed. However, in the parallel inverter structure, circulating current is inevitably generated. Circulating current increases the stress on the switch, adversely affects the current control performance, and renders load sharing difficult. The proposed method compensates for the output voltage reference of the slave module by using the high-frequency voltage so that the switching pattern of each module is matched even in asynchronous carriers. The validity of the proposed method is verified by simulations and experiments with 600 W IPMSM.