• 한국수학사학회지
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• 제12권2호
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• pp.99-118
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• 1999

This study aims to find the significance of the ancient Egyptian arithmetic in mathematics education and to analyze the educational value by practical teaching of the Egyptian multiplication. In this study, we confirmed that application of historical materials in mathematics instruction enable students to awaken their interest, to offer the opportunities of exploration, and furthermore to develop their mathematical thinking ability.

• 정보보호학회논문지
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• 제27권3호
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• pp.413-426
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• 2017

본 연구에서는 완전동형암호로 암호화된 데이터에 적용할 수 있는 가산기 및 다수개의 데이터를 가산할 때 적용할 수 있는 성능이 향상된 가산 방법을 제안한다. 제안 산술 가산기는 기존의 하드웨어 기반의 산술 가산기 중 최적 회로단계(level)를 가지는 Kogge-Stone Adder 방법을 기반으로 하며, 완전동형암호가 제공하는 암호학적 SIMD(Single Instruction for Multiple Data) 기법을 적용하기에 적합하게 설계되었다. 제안한 다수 가산 방법은 완벽한 가산 결과를 보장하는 Kogge-Stone Adder를 반복적으로 사용하여 다수개의 데이터를 가산하지 않고, 3개 이상의 수를 더해야 할 경우, Full-Adder를 이용하여 3개의 수를 최종 C(Carry-out)과 논리합의 결과인 S(Sum) 의 두 개로 줄인다. 이러한 과정을 반복하여 최종적으로 두 개의 수를 더할 경우에만 Kogge-Stone Adder를 사용하여 가산하는 방법이다. 제안 방법은 더하고자 하는 데이터의 개수가 많아질수록 성능이 비약적으로 향상되었고, 이를 실험을 통해 검증한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.486-490
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• 2004

Programmable logic controller (PLC) is widely used in manufacturing system or process control. This paper presents the design of a 32-bit microprocessor for a sequence control using an Application Specification Integrated Circuit (ASIC). The 32-bit microprocessor was designed by a VHDL with top down method; the program memory was separated from the data memory for high speed execution of 274 specified sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. And in order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32-bits. And the real time debugging as single step run, break point run was implemented. Pulse instruction, step controller, master controllers, BIN and BCD type arithmetic instructions, barrel shit instructions were implemented for many used in PLC system. The designed microprocessor was synthesized by the S1L50000 series which contains 70,000 gates with 0.65um technology of SEIKO EPSON. Finally, the benchmark was performed to show that designed 32-bit microprocessor has better performance than Q4A PLC of Mitsubishi Corporation.

• Progress in Superconductivity
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• 제6권2호
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• 한국컴퓨터산업학회논문지
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• 제3권2호
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• pp.149-158
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• 2002

본 논문에서는 광컴퓨터의 개발에 이용될 수 있는 산술논리연산회로(ALU)를 설계하고 검증한다. 전자회로 기술의 접목이 용이하고 가장 상용화가 잘된 $LiNbO_3$ 광스위칭 소자에 기반한 이 ALU는 산술논리 동작을 실행하는 연산회로, 오퍼런드와 연산결과를 저장하는 메모리 소자 그리고 명령어 선택을 위한 부가회로로 구성되며, 비트 단위 직렬 방식으로 동작하는 것이다. 본 논문에서는 또한 설계한 ALU 회로의 정확성을 검증할 수 있는 시뮬레이터를 구현하고, 일련의 기본 명령어들을 순차적으로 실행하면서 메모리와 누산기에 저장된 값의 단계적 변화를 확인하는 시뮬레이션을 통하여 설계한 ALU가 정확함을 보인다.

• Progress in Superconductivity
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• 제7권2호
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• Progress in Superconductivity
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• 제5권1호
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• Journal of the Optical Society of Korea
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• 제9권3호
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• pp.111-118
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• 2005

In this paper, a new optical parallel binary arithmetic processor (OPBAP) capable of computing arbitrary n-bit look-ahead carry full-addition is proposed and implemented. The conventional Boolean algebra is considered to implement OPBAP by using two schemes of optical logic processor. One is space-variant optical logic gate processor (SVOLGP), the other is shadow-casting optical logic array processor (SCOLAP). SVOLGP can process logical AND and OR operations different in space simultaneously by using free-space interconnection logic filters, while SCOLAP can perform any possible 16 Boolean logic function by using spatial instruction-control filter. A dual-rail encoding method is adopted because the complement of an input is needed in arithmetic process. Experiment on OPBAP for an 8-bit look-ahead carry full addition is performed. The experimental results have shown that the proposed OPBAP has a capability of optical look-ahead carry full-addition with high computing speed regardless of the data length.

• International journal of advanced smart convergence
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• 제6권2호
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• pp.24-33
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• 2017

Since 'teaching coding' or 'programming' classes for computational thinking (CT) education in K-12 are renowned around the world, a pre-service teachers' readiness for integrating CT into their teaching subjects is important due to the fact that CT is considered to be another 'R' from algoRitm for 21st century literacy, in addition to the traditional 3R (Reading, Writhing, and Arithmetic) [2] and CT roles to other disciplines. With this rationale, we designed a guided instruction based CT course for pre-service teachers. We show the effectiveness of the program with respect to the teachers' attitude toward combining CT into their teaching subjects, and mindset changes of learning computing connected with the career development of the teacher themselves. The research focused on the instructional methodology of teaching programing for non-Computer Science Education (CSE) majors who are not familiar with computer science for alleviating the cognitive load of first exposure to programming course under the CT concepts.

• 한국정밀공학회지
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• 제1권2호
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• pp.69-74
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• 1984

In this paper we present a microprocessor-based interpolator using algebraic arithmetic method. The interpolator consists of 2910 "bit-slice" microprocessor chips and 0.5K ROMs of microprogram memory. The system design is an instruction-data-based architecture with 250ns cycle time. A significant feature of the interpolator is that it has flexibility, very fast interpolatioon speed of (max) 250K pulses/sec, and performs additional functions simultaneously. Throughout the paper detailed explanations are given as to how one can design the hardware and software of the interpolator efficently. In addi- tion to hardware and software design, experimental results are pressented.ressented.