• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.7
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• pp.947-952
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• 2010

Components such as pressure vessel, hydraulic hose assembly, accumulator, hydraulic cylinder, hydraulic valve, pipe, etc., are tested under the impulse-pressure conditions prescribed in ISO and SAE standards. The impulse pressure test machine needs to have a high pressure, a precise control system and a long life. It should satisfy the requirements for fabrication of the impulse tester to generate ultra high pressure in the hydraulic system. In the impulse tester, a servo-valve control system is adopted; although the control application is convenient, it is expensive owing to the cost of developing the system. The type of the control system determines the pressure wave, which affects the components that are tested. In this study, the manufacturing process and the intensifier system design related to the flow, pressure, and the increasing rate of pressure are investigated. The results indicate the ultra high pressure waves in the system.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.48-55
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• 2000

Recently due to rapid improvement of integrated circuit design environment, size of IC design is to become large to possible design System on Chip(SoC) that one chip with multi function enclosed. Also cause to this rapid change, consumption market is require to spend smallest time for new product development. In this paper to propose a methodology can design a large size IC for save time and applied to design of MPEG Layer 2 decoder to can use audio receiver in digital broadcast system. The digital broadcast audio decoder in this paper is pointed to save hardware size as optimizing algorithm. MPEG Layer 2 decoder algorithm is include MAC to can have an effect on hardware size. So coefficients are using sign digit expression. It is for hardware optimization. If using this method can design MAC without multiplier. The designed audio decoder is using 14,000 gates hardware size and save 22% (4000 gates) hardware usage than using multiplier. Also can design MPEG Layer 2 decoder usable digital broadcast receiver for short time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.121-126
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• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• The Korean Journal of Ecology
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• v.23 no.1
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• pp.59-64
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• 2000

Heavy metal concentrations in surface sediments, seawater and oysters (Crassostrea gigas) were determined to assess heavy metal contamination in the Jinhae Bay. The ranges of cadmium, cobalt, copper, nickel, lead and zinc concentration in surface sediments were 0.1∼2.4, 12.6∼14.4, 25.3∼ 92.3, 32.4∼ 93.5, 24. 1∼81.2, 124∼477 ㎍/g, respectively. The concentrations of cadmium, copper, lead and zinc which were influenced by industrial activity were the highest in the inside of Masan Bay. Dissolved concentrations of cadmium, cobalt, copper, nickel, lead and zinc in seawater were <0.010∼0.043, 0.008∼0.120, 0.31∼0.90, 0.25∼3.10, 0.010∼0.142, 0.27∼9.04 ㎍/L, respectively. The concentrations of cadmium, cobalt, copper, nickel, lead and zinc in seawater were also the highest inside of Masan Bay, suggesting that Masan Bay is the major source of heavy metal input to the Jinhae Bay. Bioconcentration factors (BCF) of zinc, copper, cadmium, lead, cobalt and nickel in C. gigas were 647373, 280861, 145069, 44559, 13524, 2745, respectively, showing C gigas is a stronger accumulator than other bivalves.

• Transactions of the Korean hydrogen and new energy society
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• v.22 no.4
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• pp.552-558
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• 2011

A 50 kW class rotating body type wave energy converter consisted of two floating bodies and a PTO (Power Takeoff) unit is studied. As an wave energy extractor, the body is designed to have a VLCO (Variable Liquid-Column Oscillator) having a liquid filled U-tube with air chambers. Owing to the oscillation of the liquid in the U-tube caused by the air spring effect of the air chambers, the amplitude of response of the VLCO becomes significantly amplified for a target wave period. The PTO converts the rotational moment introduced from the relative motion of the hinged bodies to an hydraulic power by means of a cylinder. A high pressure accumulator, hydraulic motor and a generator are equipped in the PTO to convert the hydraulic power to electric power. A control law for adjusting the oscillation period of the VLCO is proposed for the efficient operation of the VLCO with various wave conditions. It is found that the effect of the air spring has an important role to play in making the oscillation of the VLCO match with the ocean wave. In this way, the wave energy converter equipped with the VLCO provides the most effective mode for extracting energy from the ocean wave.

• Journal of Korea Multimedia Society
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• v.8 no.2
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• pp.201-210
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• 2005

This paper proposes a power efficient 2-dimensional DCT/IDCT architecture driven by input data to be processed. The architecture achieves low power by taking advantage of the typically large fraction of zero and small-valued input processing data in video and image data compression. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit partitioned adders within multipliers and accumulators using simple input ANDing and bit-slice MASKing. The processed results from 1-D DCT/IDCT do not have unnecessary sign extension bits (SEBs), which are used for further power reduction in matrix transposer. The results extracted by bit-level transition activity simulations indicate significant power reduction compared to conventional designs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.6
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• pp.546-551
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• 2002

In this paper, a triple controlled type DDFS-driven PLL frequency synthesizer with reduced complexity is used to show its applications for broadband wireless communication systems by frequency synthesis control. Since the proposed DDFS-driven PLL synthesizer is very simplified to use only phase accumulator in DDFS, it improves the switching speed and power consumption than the conventional DDFS-driven PLL frequency synthesizer. It is appropriate for applications with requirements of broadband, low-power consumption and high switching speed, since the proposed synthesizer can cover a wide range of frequency bands by the triple frequency control parameters. Method and results of frequency control parameters assignment are shown for the several frequency bands applications such as GSM, IMT-2000, Bluetooth and PCS system.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.37-50
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• 2007

In this paper, we designed and implementation of the high speed neuron processor for real time object recognition in the making automatic system. and we designed of the PE(Processing Element) used residue number system without carry propagation for the high speed operation. Consisting of MAC(Multiplication and Accumulation) operator using residue number system and sigmoid function operator unit using MAC(Mixed Radix conversion) is designed. The designed circuits are descript by C language and VHDL(Very High Speed Integrated Circuit Hardware Description Language) and synthesized by compass tools and finally, the designed processor is fabricated in $0.8{\mu}m$ CMOS process. we designed of MAC operation unit and sigmoid proceeding unit are proved that it could run time 0.6nsec on the simulation and improved to the speed of the three times and decreased to hardware size about 50%, each order. The designed neuron processor can be implemented of the object recognition in making automatic system with desired real time processing.

• Journal of the Korean Society of Propulsion Engineers
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• v.16 no.6
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• pp.79-84
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• 2012

An experiment of rapid pressurization-induced crack propagation of solid propellant was conducted by using a windowed test chamber. A pre-cracked specimen of solid propellant is installed in the chamber, and highly compressed nitrogen gas in an accumulator pressurizes the chamber until the chamber pressure reaches set-up pressure to make the chamber depressurization. Pressure-time trace was obtained from the experimental result, and pressurization rate was defined from the trace. In this study, three pressurization rates (64.34, 73.86 and 85.44 MPa/s) are considered, and propagation lengths are measured. Also, a progression of the crack propagation recorded by a high-speed digital camera is presented.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.1-10
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• 1998

It is important to know phase offsets of a spreading code in the code division multiple access(CDMA) mobile communication systems because different phase offsets of the same spreading code are used to distinguish each base station. When the period of the code is not that long, the relative phase offset between the code and its shifted code can be found by comparing them, but as the period of the code increases it becomes difficult to find the phase offset. This paper describes a method to calculate the phase offset of a binary code based on the number theoretical approach. We define an accumulator function which plays a central role in this paper, and relationships between the functions are clarified. This number theoretical approach and their results show that this method is very easy for the phase offset calculation. Its application to the CDMA system and circuit realization of the phase offset calculation are also discussed.