• Transactions on Electrical and Electronic Materials
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• 제16권1호
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• pp.34-36
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• 2015

Amorphous SiZnSnO(SZTO) thin film transistors(TFTs) have been fabricated by RF magnetron sputtering process, and they were annealed in air and in wet ambient. The electrical performance and the structure were analyzed by I-V measurement, XPS, AFM, and XRD. The results showed improvement in device performance by wet annealing process compared to air annealing treatment, because free electron was shown to be increased due to reaction of oxygen and hydrogen generating oxygen vacancy. This is understood by the generation of free electrons. We expect the wet annealing process to be a promising candidate to contributing to high electrical performance of oxide thin film transistors for backplane device applications.

• Transactions on Electrical and Electronic Materials
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• 제16권2호
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• pp.62-64
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• 2015

We have investigated zinc tin oxide (ZTO) thin films under various silicon ratios. ZTO TFTs were fabricated by solution processing with the bottom gate structure. Furthermore, annealing process was performed at different temperatures in various annealing conditions, such as air, vacuum and wet ambient. Completed fabrication of ZTO TFT, and the performance of TFT has been compared depending on the annealing conditions by measuring the transfer curve. In addition, structure in ZTO thin films has been investigated by X-ray diffraction spectroscopy (XRD) and Scanning electron microscope (SEM). It is confirmed that the electrical performance of ZTO TFTs are improved by adopting optimized annealing conditions. Optimized annealing condition has been found for obtaining high mobility.

• Composites Research
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• 제26권2호
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• pp.123-128
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• 2013

PVDF(polyvinylidene fluoride) 섬유는 습식방사방법을 적용하여 제조하였다. PVDF 분자 내 압전 특성과 밀접한 관련을 갖는 ${\beta}$형태의 결정 함량을 높이기 위하여, 본 연구에서는 습식방사 된 섬유에 1단계 연신, 2단계 어닐링 공정으로 구성하여 후 처리를 도입하였다. 후 처리는 PVDF 고분자의 유리전이 온도($T_g$)와 용융온도($T_m$) 사이의 온도범위에서 진행하여, 최대의 ${\beta}$형태 결정을 생성 할 수 있는 열처리 조건을 최적화 하였다. 제조된 PVDF 섬유 내 분자 배향 특성과 결정 구조를 확인하기 위하여 적외선 분광 광도계(FT-IR)와 X선 회절 분석기(XRD)를 이용하여 분석하였으며, 전자현미경(SEM)을 통하여 섬유의 표면을 관찰하여 섬유의 평균직경을 확인하였다. 분석 결과, 후 처리 공정이 PVDF 결정 구조의 영향을 미치며, ${\beta}$형태의 결정 비율을 증가시킨다는 것을 확인하였다. 더불어 ${\beta}$형태 결정 향상으로 인해 기계적 강도가 증가되었으며, 압전 특성 향상까지 기대할 수 있었다.

• 한국표면공학회지
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• 제48권1호
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• pp.7-10
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• 2015

Recently, oxide TFTs has attracted a lot of interests due to their outstanding properties such as excellent environmental stability, high mobility, wide-band gap energy and high transparency, and investigated through the method using vacuum system and wet solution. In the case of the method using wet solution, process is very simple, however, annealing process should be included. In this study, to overcome the problem of annealing process, atmospheric pressure plasma was used for annealing, and the electrical characteristics such as on/off ration and mobility of device were investigated.

• 한국전기전자재료학회논문지
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• 제24권2호
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• pp.152-155
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• 2011

Even though nano-scale materials were very advantageous for various applications, there are still problems to be solved such as the stabilization of surface state and realization of low contact resistances between a semiconducting nanowire and electrodes in nano-electronics. It is well known that the effects of contacts barrier between nano-channel and metal electrodes were dominant in carrier transportation in individual nano-electronics. In this report, it was investigated the electrical properties of GaN nanorod devices after chemical etching and rapid thermal annealing for making good contacts. After KOH wet-etching of the contact area the devices showed better electrical performance compared with non-treated GaN individual devices but still didn't have linear voltage-current characteristics. The shape of voltage-current properties of GaN devices were improved remarkably after rapid thermal annealing as showing Ohmic behaviors with further bigger conductivities. Even though chemical etching of the nanorod surfaces could cause scattering of carriers, in here it was shown that the most important and dominant factor in carrier transport of nano-electronics was realization of low contact barrier between nano-channel and metal electrodes surely.

• 한국결정성장학회지
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• 제9권2호
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• pp.173-179
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• 1999

본 연구에서는 비정질 규소 박막의 결정화를 촉진시키기 위하여 표면 활성화 처리의 영향을 관찰하였다. 표면 활성화 방법으로는 습식 연마법(Wet Blasting)과 Nd:YAG 레이저의 빔을 사용하였고, 700~$800^{\circ}C$에서 관상로 열처리를 행하여 고살 결정화에 미치는 영향을 보았다. 결정화 정도의 기준으로는 XRD 분석을 통해 얻은 (111) 피크강도를 이용하였으며, 결정의 품질을 분석하기 위해 Raman 분석을 행하였다. 결정화의 표면 형상에 대한 관찰은 주사전자 현미경(SEM)을 사용하였다. 본 실험 결과 표면 활성화 처리는 비정질 규소박막의 결정화를 촉진하고, 결정의 품질을 향상시키는 것으로 확인되었다. 습식 연마법(Wet Blasting)의 경루 2 Kgf/$\textrm{cm}^2$의 압력이 가장 효과적이었고, 레이저의 에너지는 100~200mJ/$\textrm{cm}^2$가 효과적이었다. 이것은 표면활성화처리를 통하여 비정질 실리콘 박막의 표면에 strain energy가 형성되어 결정화에 필요한 엔탈피에 영향을 미친 효과 때문으로 예상된다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1993년도 춘계학술발표회
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• pp.34-34
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• 1993

• 한국표면공학회지
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• 제35권6호
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• pp.377-382
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• 2002

We investigated the appropriate wet cleaning process for Co-Ti-Si compounds formed on top of cobalt disilicide made from Co/Ti deposition and two rapid thermal annealing (RTA). We employed three wet cleaning processes, WP1 ($H_2$SO$_4$ etchant), WP2 ($NH_4$OH etchant), and WP3 which execute sequentially WP1 and WP2 after the first RTA. All samples were cleaned with BOE etchant after the second RTA. We characterized the sheet resistance with process steps by a four-point probe, the microstructure evolution by a cross detail sectional transmission electron microscope, a Auger depth profiler, and a X-ray diffractometer (XRD). We confirmed WP3 wet cleaning process were the most suitable to remove CoTiSi layer selectively.

• 한국표면공학회지
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• 제33권2호
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• pp.101-106
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• 2000

SOI (Silicon-On-Insulator) substrates were fabricated with varying annealing temperature of $25-660^{\circ}C$ by a linear annealing method, which was modified RTA process using a linear shape heat source. The annealing method was applied to Si ∥ $SiO_2$/Si pair pre-contacted at room temperature after wet cleaning process. The bonding strength of SOI substrates was measured by two methods of Razor-blade crack opening and direct tensile test. The fractured surfaces after direct tensile test were also investigated by the optical microscope as well as $\alpha$-STEP gauge. The interface bonding energy was 1140mJ/m$^2$ at the annealing temperature of $430^{\circ}C$. The fracture strength was about 21MPa at the temperature of $430^{\circ}C$. These mechanical properties were not reported with the conventional furnace annealing or rapid thermal annealing method at the temperature below $500^{\circ}C$. Our results imply that the bonded wafer pair could endure CMP (Chemo-Mechanical Polishing) or Lapping process without debonding, fracture or dopant redistribution.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.56-59
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• 2000

In this paper, we have made a comparison between secondary ion mass spectroscopy(SIMS) data by the 5kcV-15keV boron implantation and computer simulation results. In order to make electrical activation of implanted carriers, thermal annealing are carried out by RTP method for 30s at 1000$^{\circ}C$ Two dimensional doping concentration distribution from different mask dimensions under inert gas annealing, dry-, and wet-oxidation condition were calculated and simulated with microtec simulator.