• Title/Summary/Keyword: Wafer processing

검색결과 233건 처리시간 0.028초

한 개의 Lamp를 이용한 Metal Alloy용 RTP 장비 개발 (Development of the RTP System for Metal Alloy using One Lamp)

  • 최진호;이동엽
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1996년도 추계학술대회 논문집 학회본부
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    • pp.254-257
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    • 1996
  • A Rapid Thermal Processing (RTP) system operated below $500^{\circ}C$ has been designed and constructed. It uses an optical pyrometer for measuring wafer temperature, the sensing range of pyrometer is from $2.0{\mu}m$ to $2.4{\mu}m$. To remove the interference effect by IR emitted from lamps an IR filter is adapted which uses water. The best condition for Al alloy using the RTP system is $425^{\circ}C$ for ten seconds. The RTP system uses many lamps for supplying enough power in processing wafer because the absorption wavelength range of IF filter is from $1.3{\mu}m$ to $4.0{\mu}m$. However, reproducibility and uniformity is reduced due to the difference of lamp characteristics. Therefore, for improving the reproducibility and uniformity new RTP system using one lamp is designed. The new RTP system uses a focusing mirror and it focuses the light of lamp. The curverture of the focusing mirror is controlled to supply uniform power in processing wafer. The result of computer simulation shows the possibility of new RTP system using one lamp.

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레이저 세정기술을 이용한 웨이퍼의 표면세정 (Surface Cleaning of a Wafer Contaminated by Fingerprint Using a Laser Cleaning Technology)

  • 이명화;백지영;송재동;김상범;김경수
    • 한국분무공학회지
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    • 제12권4호
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    • pp.185-190
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    • 2007
  • There is a growing interest to develop a new cleaning technology to overcome the disadvantages of wet cleaning technologies such as environmental pollution and the cleaning difficulty of contaminants on integrated circuits. Laser cleaning is a potential technology to remove various pollutants on a wafer surface. However, there is no fundamental data about cleaning efficiencies and cleaning mechanisms of contaminants on a wafer surface using a laser cleaning technology. Therefore, the cleaning characteristics of a wafer surface using an excimer laser were investigated in this study. Fingerprint consisting of inorganic and organic materials was chosen as a representative of pollutants and the effectiveness of a laser irradiation on a wafer cleaning has been investigated qualitatively and quantitatively. The results have shown that cleaning degree is proportional to the laser irradiation time and repetition rate, and quantitative analysis conducted by an image processing method also have shown the same trend. Furthermore, the cleaning efficiency of a wafer contaminated by fingerprint strongly depended on a photothermal cleaning mechanism and the species were removed in order of hydrophilic and hydrophobic contaminants by laser irradiation.

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상대속도를 고려한 CMP 공정에서의 연마제거율 모델 (MRR model for the CMP Process Considering Relative Velocity)

  • 김기현;오수익;전병희
    • 소성∙가공
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    • 제13권3호
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    • pp.225-229
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    • 2004
  • Chemical Mechanical Polishing(CMP) process becomes one of the most important semiconductor processes. But the basic mechanism of CMP still does not established. Slurry fluid dynamics that there is a slurry film between a wafer and a pad and contact mechanics that a wafer and a pad contact directly are the two main studies for CMP. This paper based on the latter one, especially on the abrasion wear model. Material Removal Rate(MRR) is calculated using the trajectory length of every point on a wafer during the process time. Both the rotational velocity of a wafer and a pad and the wafer oscillation velocity which has omitted in other studies are considered. For the purpose of the verification of our simulation, we used the experimental results of S.H.Li et al. The simulation results show that the tendency of the calculated MRR using the relative velocity is very similar to the experimental results and that the oscillation effect on MRR at a real CMP condition is lower than 1.5%, which is higher than the relative velocity effect of wafer, and that the velocity factor. not the velocity itself, should be taken into consideration in the CMP wear model.

방사형 캘리브레이터률 이용한 웨이퍼 위치 인식시스템 (Wafer Position Recognition System Using Radial Shape Calibrator)

  • 이병국;이준재
    • 한국멀티미디어학회논문지
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    • 제14권5호
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    • pp.632-641
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    • 2011
  • 본 논문에서는 반도체 생산 공정 중 클리닝 공정 설비에서, 웨이퍼의 장착 위치를 인식하는 영상 인식 시스템을 제안한다. 제안한 시스템은 웨이퍼의 위치 이탈에 따른 위치오차 발생 시 이를 클리닝 설비에 전달하여, 웨이퍼 클리닝 장비의 파손을 방지하여 시스템의 신뢰성과 경제성을 높이기 위한 것이다. 제안한 방법은 기존의 시스템에서 체스보드 형태의 캘리브레이터를 사용시 발생되는 오차를 줄이기 위하여 방사형 캘리브레이터를 디자인 및 제작하고 이의 매핑합수를 구하는데 있다. 제안한 시스템은 고 신뢰성과 고 정밀의 위치인식 알고리즘을 사용하여, 효율적으로 웨이퍼 인라인 공정에 설치함을 목표로 하며 실험결과 기존의 방법에 비해 충분한 허용 기준 내에서 오차를 검출해내는 좋은 성능을 보여준다.

실리콘웨이퍼 평탄도 추정 알고리즘을 위한 디지털 컨덴츠에 관한 연구 (A study on the Digital contents for Estimated Thickness Algorithm of Silicon wafer)

  • 송은지
    • 디지털콘텐츠학회 논문지
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    • 제5권4호
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    • pp.251-256
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    • 2004
  • 반도체 집적회로를 만드는 토대가 되는 실리콘 웨이퍼의 표면은 고품질 회로를 구성하기 위해 극도의 평탄도가 요구되므로 평탄도는 양질의 웨이퍼를 보증하는 가장 중요한 요소이다. 따라서 실리콘웨이퍼 생산의 10개의 공정 중 거칠어진 웨이퍼 표면을 고도의 평탄도를 갖도록 연마하는 폴리싱공정은 매우 중요시 되는 생산라인이다. 현재 이 공정에서는 담당 엔지니어가 웨이퍼의 모형을 측정장비의 모니터에서 육안으로 관찰하여 판단하고 평탄도를 높이기 위한 제어를 하고 있다. 그러나 사람에 의한 것이므로 많은 경험이 필요하고 일일이 체크해야하는 번거로움이 있다. 본 연구는 이러한 비효율적인 작업의 효율화를 위해 웨이퍼의 모형을 디지털 컨텐츠화하여 폴리싱 공정에 있어 평탄도를 사람이 아닌 시스템에 의해 자동으로 측정하여 제어하는 알고리즘을 제안한다. 또한 제안한 전체 웨이퍼 평탄도 추정알고리즘을 토대로 실제 현장에서 쓰이는 웨이퍼 각 사이트별 평탄도를 측정하기 위한 사이트두께 추정 알고리즘을 제안한다.

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The New Generation Laser Dicing Technology for Ultra Thin Si wafer

  • Kumagai, Masayoshi;Uchiyama, N.;Atsumi, K.;Fukumitsu, K.;Ohmura, E.;Morita, H.
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2006년도 ISMP 2006
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    • pp.125-134
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    • 2006
  • Process & mechanism $\blacklozenge$ The process consists from two steps which are laser processing step and separation steop. $\blacklozenge$ The wavelength of laser beam is transmissible wavelength for the wafer. However, inside of Si wafer is processed due to temperature dependence of optical absorption coefficient Advantage & Application $\blacklozenge$ Advantages are high speed dicing, no debris contaminants, completely dry process, etc. $\blacklozenge$ The cutting edges were fine, The lifetime and endurances did not degrade the device characteristics $\blacklozenge$ A separation of a wafer with DAF was introduced as an application for SiP

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고온 확산공정에 따른 산화막의 전기적 특성 (Electrical Characteristics of Oxide Layer Due to High Temperature Diffusion Process)

  • 홍능표;홍진웅
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제52권10호
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    • pp.451-457
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    • 2003
  • The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.