• Transactions on Electrical and Electronic Materials
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• 제3권4호
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• pp.5-9
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• 2002

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. Especially, to achieve the higher density and greater performance, shallow trench isolation (STI)-CMP process has been attracted attention for multilevel interconnection as an essential isolation technology. Also, it was possible to apply the direct STI-CMP process without reverse moat etch step using high selectivity slurry (HSS). In this work, we determined the process margin with optimized process conditions to apply HSS STI-CMP process. Then, we evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions. The wafer-to-wafer thickness variation and day-by-day reproducibility of STI-CMP process after repeatable tests were investigated. Our experimental results show, quite acceptable and reproducible CMP results with a wafer-to-wafer thickness variation within 400$\AA$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.31-34
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• 2000

It is very important to understand the correlation of between inter layer dielectric(ILD) CMP process and various facility factors supplied to equipment system. In this paper, the correlation between the various facility factors supplied to CMP equipment system and ILD CMP process were studied. To prevent the partial over-polishing(edge hot-spot) generated in the wafer edge area during polishing, we analyzed various facilities supplied at supply system. With facility shortage of D.I. water(DIW) pressure, we introduced an adding purified $N_2(PN_2)$ gas in polishing head cleaning station for increasing a cleaning effect. DIW pressure and PN2 gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and PN2 gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% wafer edge over-polishing. In this study, we acknowledged that facility factors supplied to equipment system played an important role in ILD-CMP process.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.355-356
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• 2008

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 춘계학술대회 논문집
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• pp.749-750
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• 2007

• 한국세라믹학회:학술대회논문집
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• 한국세라믹학회 2003년도 추계총회 및 연구발표회 초록집
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• pp.83.2-83
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• 2003

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2010년도 추계학술대회 논문집
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• pp.695-696
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• 2010

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.263-264
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• 2011

• Tribology and Lubricants
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• 제28권6호
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• pp.272-277
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• 2012

Finite element analysis was carried out using wafer-scale and particle-scale models to understand the mechanism of the fast removal rate(edge effect) at wafer edges in the chemical-mechanical polishing process. This is the first to report that a particle-scale model can explain the edge effect well in terms of stress distribution and magnitude. The results also revealed that the mechanism could not be fully understood by using the wafer-scale model, which has been used in many previous studies. The wafer-scale model neither gives the stress magnitude that is sufficient to remove material nor indicates the coincidence between the stress distribution and the removal rate along a wafer surface.

• 한국기계가공학회지
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• 제11권6호
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• pp.48-54
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• 2012

In recent years, developments in the semiconductor and electronic industries have brought a rapid increase in the use of large size silicon. However, for many companies, it is hard to produce 400mm or 450mm wafers, because of excesive funds for exchange the equipments. Therefore, it is necessary to investigate 300mm wafer to obtain a better efficiency and a good property rate. Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This research investigated the surface characteristics that apply variable machining conditions and Taguchi Method was used to obtain more flexible and optimal condition. In this study, the machining conditions have head speed, oscillation speed and polishing time. By using optimum condition, it achieves a ultra precision mirror like surface.

• 한국정밀공학회지
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• 제21권10호
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• pp.26-33
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• 2004

Ultra precision grinding technology has been developed from the refinement of the abrasive, the development of high stiffness equipment and grinding skill. The conventional wafering process which consists of lapping, etching, 1 st, 2nd and 3rd polishing has been changed to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Furthermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focuses on the flatness of the ground wafer. Generally, the ground wafer has concave pronto because of the difference of wheel path density, grinding temperature and elastic deformation of the equipment. Wafer tilting is applied to avoid non-uniform material removal. Through the geometric analysis of wafer grinding process, the profile of the ground wafer is predicted by the development of profile simulator.