• Title/Summary/Keyword: VPP

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A High Swing Range, High Bandwidth CMOS PGA and ADC for IF QPSK Receiver Using 1.8V Supply

  • Lee, Woo-Yol;Lim, Jong-Chul;Park, Hee-Won;Hong, Kuk-Tae;Lee, Hyeong-Soo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.4
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    • pp.276-281
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    • 2005
  • This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.

A Unified Voltage Generator Which Merges the Pumping Capacitor of Boosted Voltage Generator and Substrate Voltage Generator (내부 승압 전원 발생기와 기판 인가 전원 발생기의 펌핑 수단을 공유한 전원 전압 발생기)

  • 신동학;장성진;전영현;이칠기
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.11
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    • pp.45-53
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    • 2003
  • This paper describes a Unified Voltage Generator that merges the pumping capacitors of boosted voltage generator (VPP) and substrate voltage generator (VBB) for DRAM. This unified voltage generator simultaneously supplies VPP and VBB voltages by using one pumping capacitor and one oscillator. The proposed generator is realized by 0.14${\mu}{\textrm}{m}$DRAM process. The generator reduces the power consumption to 30%, the area of total generator to 40% and the area of pumping capacitor to 29.6%, and improves the pumping efficiency to 13.2% at 2.0V supply voltage. In addition, the generator adopts the charge recycling technique for precharging the pumping capacitor during the period of precharge, thatcan reduces the precharge current to 75%.

Measurement of Thrust Induced by the Dielectric Barrier Discharge in Cylinder Pipes (실린더 내부 유전체 장벽방전에 의해 발생된 추력 측정)

  • Joo, Chan Kyu;Kim, Jong Hoon;Furudate, Michiko Ahn
    • Journal of Aerospace System Engineering
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    • v.11 no.6
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    • pp.56-63
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    • 2017
  • Thrust force induced by the dielectric barrier discharge inside of cylinder pipes is measured for various conditions. The input peak-to-peak voltage and frequency are varied from 2 to 9 kVpp and from 5 to 15 kHz, respectively. The height of cylinder is varied from 50 to 100 mm. The results of the measurements show that the magnitude of the generated thrusts increases as the voltage and the frequencies increase. It also shows that the generated thrusts are decreased according to the increase in the height of the cylinder. The cause of the thrust decrease is discussed in terms of energy losses due to the frictions on the wall surface.

Effect of Supplementation of Fermented Milk Containing Active Peptides(IPP, VPP) in Accordance with Medical Nutrition Therapy in Pre- and Hypertension Subjects (고혈압 전단계 및 고혈압 환자에서 의학영양치료와 병행한 생리활성 펩티드 함유 유산균 발효유 섭취가 혈압에 미치는 영향)

  • Kim, Ji-Young;Kim, Yun-Young;Kim, Hye-Rang;Yun, Sung-Seob;Kim, Wan-Sik;Yea, Hyun-Soo;Chung, Jin-Young;Lee, In-Hoe;Choue, Ryo-Won
    • Journal of the East Asian Society of Dietary Life
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    • v.18 no.6
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    • pp.918-926
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    • 2008
  • It is well known non-drug therapy for hypertension patients can reduce blood pressure. These types of therapy include maintaining ones ideal body weight, quitting smoking, consuming large amounts of fruits and vegetables consuming low levels of saturated fat and salt and regular exercise. Fermented milk protein derived biologically active peptides such as isoleucine-proline-proline_(IPP) or valine-proline-proline_(VPP) have been shown to lower blood pressure in hypertensive subjects. This study was conducted to investigate the antihypertensive effects of medical nutritional therapy _(MNT) in accordance with the consumption of fermented milk enriched with IPP and VPP. To accomplish this, we conducted a randomized case-controlled study of 43 subjects who had blood pressure levels greater than 120/80 mmHg. The subjects in the study group were randomly allocated into two groups, an MNT + fermented milk (100mL/day) group (n=21) and an MNT+L. helveticus fermented milk with tripeptides (IPP=2.2mg, VPP=2.6mg/100mL) group (n=22). The MNT included weight management, reduction of sodium, total fat and saturated fat intake, increased intake of fruits and vegetables, and increased intake of low fat dairy products. The treatments were administered for 12 weeks during which time no drug interventions were conducted. The daily intakes of total calories, fats, cholesterol and Na decreased significantly after 12 weeks of MNT in the control and the experimental groups. In addition, the systolic blood pressure de creased significantly in the control and experimental groups; however, the diastolic blood pressure only decreased significantly in the experimental group. Overall, the results of this study indicate that the intake of fermented milk containing IPP and VPP in conjunction with MNT exerted positive effects on the blood pressure of pre- and hypertensive subjects.

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Design of Synchronous 256-bit OTP Memory (동기식 256-bit OTP 메모리 설계)

  • Li, Long-Zhen;Kim, Tae-Hoon;Shim, Oe-Yong;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.7
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    • pp.1227-1234
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    • 2008
  • In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

A design on low-power and small-area EEPROM for UHF RFID tag chips (UHF RFID 태그 칩용 저전력, 저면적 비동기식 EEPROM 설계)

  • Baek, Seung-Myun;Lee, Jae-Hyung;Song, Sung-Young;Kim, Jong-Hee;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.12
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    • pp.2366-2373
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    • 2007
  • In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

A 200MHz high speed 16M SDRAM with negative delay circuit (부지연 회로를 내장한 200MHz 고속 16M SDRAM)

  • 김창선;장성진;김태훈;이재구;박진석;정웅식;전영현
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.4
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    • pp.16-25
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    • 1997
  • This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.

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Effect of Imidazole and Surfactant on the Opto-Electrical Properties of PEDOT Thin Films via Vapor Phase Polymerization (이미다졸과 계면활성제가 기상중합법으로 제조된 PEDOT 박막의 광-전기적 특성에 미치는 영향)

  • Khadka, Roshan;Yim, Jin-Heong
    • Polymer(Korea)
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    • v.39 no.3
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    • pp.461-467
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    • 2015
  • This paper reports the combined effects of the triblock copolymer surfactant poly(ethylene glycol)-poly(propylene glycol)-poly(ethylene glycol) (PEG-PPG-PEG) and imidazole on the opto-electrical and mechanical properties of poly(3,4-ethylenedioxythiophene) (PEDOT)-based thin films prepared via vapor phase polymerization (VPP) using ferric p-toluenesulfonate as a catalyst. Various PEDOT-based thin films were synthesized using PEG-PPG-PEG and imidazole alone and in combination to compare and correlate their effects on film properties. The improved conductivity of the PEDOT films was higher than $1300S{\cdot}cm^{-1}$ when the surfactant and imidazole were used together. The PEG-PPG-PEG chain length was also varied to identify the best conditions for the VPP-based preparation of PEDOT thin films.

Rectifier with Comparator Using Unbalanced Body Biasing to Control Comparing Time for Wireless Power Transfer (비대칭 몸체 바이어싱 비교기를 사용하여 비교시간을 조절하는 무선 전력 전송용 정류기)

  • Ha, Byeong Wan;Cho, Choon Sik
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.11
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    • pp.1091-1097
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    • 2013
  • This paper presents a rectifier with comparator using unbalanced body biasing in $0.11{\mu}m$ RF CMOS process. It is composed of MOSFETs and two comparators. The comparator is used to reduce reverse leakage current which occurs when the load voltage is higher than input voltage. For the comparator, unbalanced body biasing is devised. By using unbalanced body biasing, reference voltage for comparator changing from high state to low state is increased, and it reduces time interval for leakage current to flow. 13.56 MHz 2 Vpp signal is used for input and $1k{\Omega}$ resistor and 1 nF capacitor are used for output load for simulation and experimental environment. In simulation environment, voltage conversion efficiency(VCE) is 87.5 % and Power conversion efficiency(PCE) is 50 %. When the rectifier is measured, VCE shows 90.203 % and PCE shows 45 %.

Design of a DC-DC Converter for CMOS Image Sensors in Bio-sensor Chips (바이오센서용 CMOS 이미지 센서를 위한 DC-DC Converter 설계)

  • Park, Heon;Ha, Pan-Bong;Kim, Young-Hee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.9 no.6
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    • pp.553-558
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    • 2016
  • A DC-DC converter for CMOS image sensors in bio-sensor chips is proposed. The DC-DC converter generates a PCP voltage, that is an on voltage of a pixel, and an NCP voltage, that is an off voltage of a pixel. The PCP voltage with a ripple voltage of within 1.33V is obtained from a positive charge pump of VPP (=5V) with a ripple voltage of 45.35 by using a regulator. Also, the NCP voltage with a ripple voltage of 0.05mV is obtained from a negative charge pump of VNN (=-2V) with a ripple voltage of 62.8 by using a regulator.