• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.11
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• pp.2113-2120
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• 2015

This paper presents an integrated receiver to support multimode broadcasting standards such as DVB-T2, DVB-C2, and DVB-S2 in a single platform. The integrated receiver consists of a tuner block, a receiver engine, a frame processor, and an A/V decoder. The receiver engine includes a channel decoding engine and a demodulation engine to perform OFDM and APSK demodulations. The frame processor performs deinterleaving and BB frame decoding functions. The demodulator engine and the frame processor are implemented in two FPGA devices and DSP-based embedded software, respectively. To verify the functionality of the integrated receiver, it is tested in the laboratory. Commercial PC-based modulators are used to generate the DVB-T2, DVB-C2, and DVB-S2 modulated signals. The integrated receiver was tested under various operation modes as specified in the standards such as DVB-T2, DVB-C2, and DVB-S2 and showed successful operation in all the scenarios tested.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.16 no.1
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• pp.157-165
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• 2017

Intelligent transportation systems are currently being developed for elemental technology development of cooperative intelligent transport systems, which enable vehicles to communicate with each other or reduce the risk of traffic accidents, We have been defining and standardizing services according to the purpose of solving traffic safety problems depending on countries. Therefore, in this study, the developed countries of V2X(vehicle-to-everything) based on USA, Europe, Japan, etc., analyzed the service cases selected in the field demonstration stage after completion of the element technology devanalyzed the service cases selected in the field demonstration stage after completion of the element technology development, and to suggest the direction of futureelopment, and to suggest the direction of future policy direction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.443-450
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• 2016

The linearization technique for low noise amplifier (LNA) has been implemented in standard $0.18-{\mu}m$ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient ($g_{m2}$) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent IIP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss ($S_{11}$) and output return loss ($S_{22}$) are kept below - 10 dB and -15 dB, respectively. The reverse isolation ($S_{12}$) is better than -50 dB.

• Communications for Statistical Applications and Methods
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• v.4 no.3
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• pp.645-661
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• 1997

연속형 변수들의 상관관계와 범주형 변수들의 연관성 측도들을 비교 연구하였다. 이 연구를 위하여 연속형 변수들이며 +1에서 -1까지 완벽한 상관관계를 갖고 있는 2 변량 정규분포를 이용하여 2$\times$2 분할표와 확장하여 일반적인 I$\times$J 분할표를 대신하는 3$\times$3 분할표를 생성하였다. 2 차원 분할표에서 정의된 연관성 측도들을 구하여 논의하였는데 2$\times$2 분할표에서는 교차적비 $\alpha$ 통계량과 교차적비의 함수로 표현되는 Yule [1912]의 Q와 Y의 통계량 그리고 상관계수 R 통계량과 R 통계량의 함수인 P 통계량을 설명하고 생성된 분할표에서 구한 통계량값을 분석하였으며, 3$\times$3 분할표에서는 Pearson의 독립성 검정통계량 $X^2$의 함수로 표현되는 P. T. V 통계량과 Goodman과 Kruskal [1954]의 $\lambda_{C/R}$통계량과 Light와 Margolin [1971]의 $\tau_{R/C}$ 통계량을 설명하고 그 값들을 Pearson의 상관계수와 비교 분석하였다.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.283-286
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• 1999

A 2㎓, low noise, low power CMOS voltage-controlled oscillator (VCO) with an integrated LC resonator is presented. The design of VCO relies heavily on the on-chip spiral inductor. An optimized spiral inductor with Q-factor of nearly 8 is achieved and used for the VCO. The simulated result of phase noise is as low as -l14 ㏈c/Hz at an offset frequency of a 600KHz from a 2㎓ carrier frequency. The VCO is tuned with standard available junction capacitors, resulting in an about 400MHz tuning range (20%). Implemented in a five-metal 0.25${\mu}{\textrm}{m}$ standard CMOS process, the VCO consumes only 2㎽ from a single 2.5V supply. It occupies an active area of 620${\mu}{\textrm}{m}$$\times$720${\mu}{\textrm}{m}$.

• Journal of Communications and Networks
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• v.14 no.2
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• pp.213-221
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• 2012

The architecture of an interconnection network is usually represented by a graph, and a graph G is bipancyclic if it contains a cycle for every even length from 4 to ${\mid}V(G){\mid}$. In this article, we analyze the conditional edge-fault-tolerant properties of an enhanced hypercube, which is an attractive variant of a hypercube that can be obtained by adding some complementary edges. For any n-dimensional enhanced hypercube with at most (2n-3) faulty edges in which each vertex is incident with at least two fault-free edges, we showed that there exists a fault-free cycle for every even length from 4 to $2^n$ when n($n{\geq}3$) and k have the same parity. We also show that a fault-free cycle for every odd length exists from n-k+2 to $2^n-1$ when n($n{\geq}2$) and k have the different parity.

• Journal of Satellite, Information and Communications
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• v.8 no.1
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• pp.54-60
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• 2013

The need for high performance of on-board computer (OBC) is essential due to the growing requirements and diversified missions, and so OBC has been developed on the basis of the standard design and reconfigurable modularization in order to improve the utilization of OBC for different missions. The processor in OBC of next generation satellite which is currently developed by KARI is adopted the LEON2-FT/AT697F processor based SPARC v8 as main processor and controls various devices such as SpaceWire, MIL-STD-1553B and CAN through PCI on the standardized communication chips. This paper presents the architecture and design of system software for LEON2-FT processor based on PCI, and development of PCI software component. Also it describes the porting of VxWorks 6.5 for LEON2-FT and the test under the simulation environment for LEON2-FT and PCI with communication chips.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1112-1119
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• 2006

In this paper, mutually coupled oscillator is employed to improve phase noise. Mutually coupled structure oscillator couples two oscillator's phase shifted output signals, that is fabricated using teflon board which has dielectric constant of 2.5 and Surface Mount Gallium Arsenide FET devices. And this paper proposed the structure to bias adjustment for the phase condition of mutually couples. When one oscillator has bias point of 4.4 V and 37 mA, it's output signal has phase noise characteristic of -96.37 dBc(@9305 MHz, offset frequency 100 KHz), -73.46 dBc(10 kHz). and After it's output signal mutually coupled the other's output signal that has bias point of 8.1 V and 69 mA, it has superior phase noise characteristic of -106.7 dBc(@9305 MHz, offset frequency 100 kHz), -81 dBc(10 kHz).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2A
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• pp.209-215
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• 2010

This paper describes a design of variable-length FFT/IFFT processor (VL_FCore) for OFDM-based multi-standard communication systems. The VL_FCore adopts in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate various FFT lengths in the range of $N=64{\times}2^k\;(0{\leq}k{\leq}7)$. To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The VL_FCore synthesized with a $0.35-{\mu}m$ CMOS cell library has 23,000 gates and 32 Kbytes memory, and it can operate with 75-MHz@3.3-V clock. The 64-point and 8,192-point FFT's can be computed in $2.25-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of various OFDM-based systems.