• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2013.10a
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• pp.222-224
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• 2013

국제항로표지협회(IALA)의 VTS장비에 대한 운영 및 기술성능 요구사항에 관한 권고안 V-128에 대한 소개와 함께 향후 개정이 예상되는 주요 개정내용을 항목별로 검토한다. 그리고 이 개정내용이 향후 국내외 VTS시장에 어떠한 영향을 가져올지 유의미한 항목에 대한 예상해본다. 마지막으로 이와 같은 국제권고안 개정작업에 있어서 자국의 목소리를 높이기 위한 적극적인 참여를 촉구하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.128.2-128.2
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• 2014

Long-wave infrared detectors using the type-II InAs/GaSb strained superlattice (T2SL) material system with the nBn structure were designed and fabricated. The band gap energy of the T2SL material was calculated as a function of the thickness of the InAs and GaSb layers by the Kronig-Penney model. Growth of the barrier material (Al0.2Ga0.8Sb) incorporated Te doping to reduce the dark current. The full width at half maximum (FWHM) of the 1st satellite superlattice peak from the X-ray diffraction was around 45 arc sec. The cutoff wavelength of the fabricated device was ${\sim}10.2{\mu}m$ (0.12eV) at 80 K while under an applied bias of -1.4V. The measured activation energy of the device was ~0.128 eV. The dark current density was shown to be $1.2{\times}10^{-5}A/cm^2$ at 80 K and with a bias -1.4 V. The responsivity was 1.9 A/W at $7.5{\mu}m$ at 80K and with a bias of -1.9V.

• Journal of Magnetics
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• v.13 no.4
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• pp.128-131
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• 2008

We have investigated the electronic structures and magnetic properties of both undoped and doped bcc Ni using the full-potential linearized augmented plane wave (FLAPW) band method. A ferromagnetic ground state is obtained at the equilibrium volume of bcc Ni. When the system is under strain, the nonmagnetic ground state is stabilized. When the Ni is doped with V, the $Ni_{16-x}V_x$ material loses its magnetic properties when x > 2. We have also discussed the possible superconducting properties of $Ni_{16-x}V_x$.

• Journal of Korea Foundry Society
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• v.10 no.2
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• pp.119-128
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• 1990

• Nuclear Engineering and Technology
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• v.6 no.2
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• pp.112-128
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• 1974

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2633-2640
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• 2009

We design a small-area, low-power, and high-speed EEPROM for touch screen controller IC. As a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed, and high-voltage switching circuits repeated in the EEPROM core circuit are optimized. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. The layout size of the designed 128-KBit EEPROMIP is $662.31{\mu}m{\times}1314.89{\mu}m$.

• Proceedings of the Korean Vacuum Society Conference
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• 2001.07a
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• pp.128-128
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• 2001

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.859-862
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• 1999

We designed a 128-tap FIR filter for a modem which complies with ITU-T V.32. We adopted pipeline technique and realized delay-taps with two ring-buffers. The multiplier in this filter carries out 2's complement fixed-point multiplication of 14bit $\times$ 16bit. The designed filter is expected to operate at 50MHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.43-53
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• 2002

In this paper, a new dynamic D-flip-flop which does not suffer from charge sharing and glitch problems is proposed. And a dual-modulus divide-by-128/129 prescaler has been designed with the proposed D-flip-flops using a 0.6$0.6{\mu}m$ CMOS technology. Eleven-transistor architecture enables it to operate at the higher frequency range and the transistor merging technique contributes to the reduction of power consumption. At 5V supply voltage, the simulated maximum operating frequency and the current consumption of the divide-by-128/129 prescaler are 1.97GHz and 7.453mA, respectively.

• Transactions on Semiconductor Engineering
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• v.2 no.1
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• pp.1-8
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• 2024

When processing depthwise separable convolution, low utilization of processing elements (PEs) is one of the challenges of systolic array (SA). In this study, we propose a new SA architecture to maximize throughput in depthwise convolution. Moreover, the proposed SA performs subsequent pointwise convolution on the idle PEs during depthwise convolution computation to increase the utilization. After the computation, we utilize unused PEs to boost the remaining pointwise convolution. Consequently, the proposed 128x128 SA achieves a 4.05x and 1.75x speed improvement and reduces the energy consumption by 66.7 % and 25.4 %, respectively, compared to the basic SA and RiSA in MobileNetV3.