Transactions on Semiconductor Engineering (반도체공학회 논문지)

The Institute of Semiconductor Engineers (반도체공학회)
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Multithreaded and Overlapped Systolic Array for Depthwise Separable Convolution

깊이별 분리 합성곱을 위한 다중 스레드 오버랩 시스톨릭 어레이

  • Jongho Yoon (Department of Electrical Engineering, Pohang University of Science and Technology) ;
  • Seunggyu Lee (Hyosung Ventures) ;
  • Seokhyeong Kang (Department of Electrical Engineering, Pohang University of Science and Technology)
  • Received : 2023.12.15
  • Accepted : 2024.01.04
  • Published : 2024.01.31
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Abstract

When processing depthwise separable convolution, low utilization of processing elements (PEs) is one of the challenges of systolic array (SA). In this study, we propose a new SA architecture to maximize throughput in depthwise convolution. Moreover, the proposed SA performs subsequent pointwise convolution on the idle PEs during depthwise convolution computation to increase the utilization. After the computation, we utilize unused PEs to boost the remaining pointwise convolution. Consequently, the proposed 128x128 SA achieves a 4.05x and 1.75x speed improvement and reduces the energy consumption by 66.7 % and 25.4 %, respectively, compared to the basic SA and RiSA in MobileNetV3.

깊이별 분리 합성곱 (Depthwise Separable Convolution)을 처리할 때, processing element (PE)의 저활용성은 시스톨릭 어레이 (SA)의 한계점 중 하나이다. 본 연구에서는 깊이별 합성곱의 처리량을 극대화하기 위한 새로운 SA 아키텍처를 제안한다. 더불어, 제안된 SA 는 깊이별 합성곱 계산 중에 유휴 PE 에서 후속 점별 합성곱 (pointwise convolution)을 수행하여 활용도를 증가시킨다. 모든 깊이별 합성곱 연산 후에는 모든 PE 를 활용하여 나머지 점별 합성곱 연산의 속도를 향상시킨다. 결과적으로, 제안된 128×128 SA 는 MobileNetV3 연산 시, 기본 SA 및 RiSA 와 비교하여 속도가 4.05 배, 1.75 배 향상되고, 에너지 소비량을 각각 66.7 %, 25.4 % 감소한다.

Keywords

Acknowledgement

The EDA Tool was supported by the IC Design Education Center.

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