• 제목/요약/키워드: Two Difference Voltage

검색결과 278건 처리시간 0.027초

고압전동기 고정자권선 결함 부분방전패턴 (Pattern of partial discharge for stator windings fault of high voltage motor)

  • 박재준;김희동
    • 정보학연구
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    • 제7권1호
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    • pp.155-161
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    • 2004
  • 정상적인 기계의 동작동안, 부분방전측정이 고전압전동기 고정자권선을 모의하여 터빈제너레이터 분석기(TGA)를 이용하여 실행하였다. 모의한 고정자권선에 인가된 전압은 4.47[kV]와 6.67[kV]을 인가하였다. 모의 고정자권선을 갖는 전동기들은 단자함에 80[pF]용량성 커풀러를 설치하였다. 인가전압 위상각을 고려한 부분방전패턴의 경우 2차원, 3차원적으로 보여주었다. TGA는 정규화된 펄스수(NGN)DHK 부분방전펄스크기(Qm)으로서 두개의 정량화된량을 나타내었다. 결론적으로, 우리는 모의한 고정자권선에 대한 내부방전과 표면방전의 차이를 TGA을 이용하여 식별할 수 있었다. 고정자권선의 결함에 대한 특징을 추출하기 위한 기법으로서 이산웨이블렛 변환기법 및 주파수분석법을 이용하여 결함신호에 대한 특징을 추출할 수 있었다.

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ZnO에서 질소 불순물에 의한 p-type Capacitance (P-type Capacitance Observed in Nitrogen-doped ZnO)

  • 유현근;김세동;이동훈;김정환;조중열
    • 전기학회논문지
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    • 제61권6호
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    • pp.817-820
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    • 2012
  • We studied p-type capacitance characteristics of ZnO thin-film transistors (TFT's), grown by metal organic chemical vapor deposition (MOCVD). We compared two ZnO TFT's: one grown at $450^{\circ}C$ and the other grown at $350^{\circ}C$. ZnO grown at $450^{\circ}C$ showed smooth capacitance profile with electron density of $1.5{\times}10^{20}cm^{-3}$. In contrast, ZnO grown at $350^{\circ}C$ showed a capacitance jump when gate voltage was changed to negative voltages. Current-voltage characteristics measured in the two samples did not show much difference. We explain that the capacitance jump is related to p-type ZnO layer formed at the $SiO_2$ interface. Current-voltage and capacitance-voltage data support that p-type characteristics are observed only when background electron density is very low.

Power Enhance Effect on the Hybrid Cell Based on Direct Current Nanogenerator and an Organic Photovoltaic Device

  • 윤규철;신경식;이근영;이주혁;김상우
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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    • pp.298-298
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    • 2013
  • Finding renewable and clean energy resources is essential research to solve global warming and depletion of fossil fuels in modern society. Recently, complex harvesting of energy from multiple sources is available in our living environments using a single device has become highly desirable, representing a new trend in energy technologies. We report that when simultaneously driving the fusion and composite cells of two or more types, it is possible to make an affect the other cells to obtain a greater synergistic effect. To understand the coupling effect of photovoltaic and piezoelectric device, we fabricate the serially integrated hybrid cell (s-HC) based on organic solar cell (OSC) and piezoelectric nanogenerator (PNG). The size of increased voltage peaks when OSC and PNG are working on is larger than the case when only PNG is working. This voltage difference is the Voc change of OSC, not the voltage change of PNG and current density difference between these two cases is manifested more clearly. When the OSC and PNG are working in s-HC at the same time, piezoelectric potential (VPNG) is generated in ZnO and theoretical total voltage is sum of voltage of an OSC (VOSC) and VPNG. However, electrons from OSC are influenced by piezoelectric potential in ZnO and current loss of OSC in whole circuit decreases. As a result, VOSC increases temporarily. Current shows the similar behavior. PNG acts a resistance in the whole circuit and current loss occurs when the electrons from OSC pass through the PNG. But piezoelectric potential recover current loss and decrease the resistance of PNG. Our PNG can maintain piezoelectric potential when the strain is held owing to the LDH layer while general PNG cannot maintain piezoelectric potential. During the section that strain is held, voltage enhancement effect is maintained and same effect appeared even turn off the light. Actually at this time, electrons in ZnO nanosheets move to LDH and trapped by the positive charges in this layer. After this strain is held, piezoelectric potential of ZnO nanosheets is disappeared but potential difference which is developed by negative charge dominant LDH layer is remained. This potential acts similar role like piezoelectric potential in ZnO. Electrons from the OSC also are influenced by this potential and the more current flows.

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동기위상 측정장치를 이용한 전력계통 위상각 측정 (Measurement of Phasor Angles of Power System using Synchronized Phasor Measurement System)

  • 이경극;이재욱;왕재명;추진부
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 추계학술대회 논문집 학회본부 A
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    • pp.55-57
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    • 2000
  • This paper presents the measurement of phasor angle of power system using Synchronized Phasor Measurement System(SPMS). SPMS includes the GPS receiver, so it can add the exact time information to the data acquired from the power system by SPMS. Using that data, we can compare the difference of phasor angles of voltages currents acquired at the exactly same time, and monitor the RMS values of voltage and current. In this paper, we present the difference of voltage angles between 345kV Sinjechon S/S and 345kV Asan S/S, where two SPMS were installed separately, and prove their performance by comparing to simulation result of PSS/E.

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A Nano-power Switched-capacitor Voltage Reference Using MOS Body Effect for Applications in Subthreshold LSI

  • Zhang, Hao;Huang, Meng-Shu;Zhang, Yi-Meng;Yoshihara, Tsutomu
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권1호
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    • pp.70-82
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    • 2014
  • A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

배터리 기반 2단 충전 9 kJ/s 고전압 충전기 설계 (Design of 9 kJ/s High Voltage LiPo Battery based 2-stage Capacitor Charger)

  • 조찬기;가재예;류홍제
    • 전력전자학회논문지
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    • 제24권4호
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    • pp.268-272
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    • 2019
  • A lithium polymer battery-based 9 kJ/s high-voltage capacitor charger, which comprises two stages, is proposed. A modified LCC resonant converter and resonant circuit are introduced at the first and second stages, respectively. In the first stage, the methods for handling low-voltage and high-current batteries are considered. Delta-wye three-phase transformers are used to generate a high output voltage through the difference between the phase and line-to-line voltages. Another method is placing the series resonant capacitor of the LCC resonant components on the transformer secondary side, which conducts considerably low current compared with the transformer primary side. On the basis of the stable operation of the first charging stage, the secondary charging stage generates final output voltage by using the resonance. This additional stage protects the rectifying diodes from the negative voltage when the output capacitor is discharged for a short time. The inductance and capacitance of the resonance components are selected by considering the resonance charging time. The design procedure for each stage with the aforementioned features is suggested, and its performance is verified by not only simulation but also experimental results.

$2{\times}3$구조의 매트릭스형 초전도 한류기의 트리거 코일 및 션트 저항에 따른 특성 (Characteristics of Matrix Type SFCL with $2{\times}3$ Array According to the Trigger Coil and Shunt Resistance)

  • 정병익;최효상
    • 전기학회논문지P
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    • 제58권1호
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    • pp.85-89
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    • 2009
  • We investigated the quench characteristics in accordance with increase of turns number of trigger coil and shunt resistance of matrix-type superconducting fault current limiter (SFCL) with $2{\times}3$ array. The matrix-type SFCL consists of the trigger part to apply magnetic field and the current-limiting part to limit fault current. The fault current limiting characteristics according to the increase of magnetic field and applied voltage were nearly same. This is because the application of magnetic field hasn't an affect on total impedance of the SFCL. When turns number of a reactor increased, the voltage difference between two superconducting units in the current-limiting part according was decreased. The resistance difference generated in two superconducting units was also decreased. Therefore, we confirmed that the differences of the critical behaviors between superconducting units were reduced by application of magnetic field. By this results, we could decide the optimum turns number of reactor to apply magnetic field.

An Optimized Stacked Driver for Synchronous Buck Converter

  • Lee, Dong-Keon;Lee, Sung-Chul;Jeong, Hang-Geun
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권2호
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    • pp.186-192
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    • 2012
  • Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

5-GHz Delay-Locked Loop Using Relative Comparison Quadrature Phase Detector

  • Wang, Sung-Ho;Kim, Jung-Tae;Hur, Chang-Wu
    • Journal of information and communication convergence engineering
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    • 제2권2호
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    • pp.102-105
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    • 2004
  • A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 um Standard CMOS process and it operates at 5 GHz frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

Stability Comparison of New Simplified Speed Sensorless Vector Control Systems for Induction Motors

  • Mangindaan, Glanny M.Ch.;Tsuji, Mineo;Hamasaki, Sin-Ichi
    • Journal of international Conference on Electrical Machines and Systems
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    • 제3권2호
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    • pp.126-131
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    • 2014
  • This paper discusses stability of new simplified sensorless vector control systems of induction motors (IM). The simplified sensorless systems estimate the flux angle by using the output voltage of d-axis PI current controller to achieve the q-axis flux zero. Two simplified sensorless systems are studied. The difference of two systems is the presence or absence of a q-axis PI current controller. The systems stability is compared by deriving linear state equations and showing root loci and unstable regions. Furthermore, transient responses and experiment results make clear the stability of the proposed system.