• 한국정보전자통신기술학회논문지
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• 제11권6호
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• pp.742-750
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• 2018

본 논문에서는 $0.13{\mu}m$ BCD 공정 기반에서 5V MOS 소자만 사용하여 zero layer FTP 셀이 가능하도록 하기 위해 tunnel oxide 두께를 기존의 $82{\AA}$에서 5V MOS 소자의 gate oxide 두께인 $125{\AA}$을 그대로 사용하였고, 기존의 DNW은 BCD 공정에서 default로 사용하는 HDNW layer를 사용하였다. 그래서 제안된 zero layer FTP 셀은 tunnel oxide와 DNW 마스크의 추가가 필요 없도록 하였다. 그리고 메모리 IP 설계 관점에서는 designer memory 영역과 user memory 영역으로 나누는 dual memory 구조 대신 PMIC 칩의 아날로그 회로의 트리밍에만 사용하는 single memory 구조를 사용하였다. 또한 BGR(Bandgap Reference Voltage) 발생회로의 start-up 회로는 1.8V~5.5V의 전압 영역에서 동작하도록 설계하였다. 한편 64비트 FTP 메모리 IP가 power-on 되면 internal reset 신호에 의해 initial read data를 00H를 유지하도록 설계하였다. $0.13{\mu}m$ Magnachip 반도체 BCD 공정을 이용하여 설계된 64비트 FTP IP의 레이아웃 사이즈는 $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$)이다.

• Current Photovoltaic Research
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• 제7권4호
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• pp.125-129
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• 2019

Recently, carrier-selective contact solar cells have attracted much interests because of its high efficiency with low recombination current density. In this study, we investigated the effect of phosphorus doped amorphous silicon layer's characteristics on the passivation properties of tunnel oxide passivated carrier-selective contact solar cells. We fabricated symmetric structure sample with poly-Si/SiOx/c-Si by deposition of phosphorus doped amorphous silicon layer on the silicon oxide with subsequent annealing and hydrogenation process. We varied deposition temperature, deposition thickness, and annealing conditions, and blistering, lifetime and passivation quality was evaluated. The result showed that blistering can be controlled by deposition temperature, and passivation quality can be improved by controlling annealing conditions. Finally, we achieved blistering-free electron carrier-selective contact with 730mV of i-Voc, and cell-like structure consisted of front boron emitter and rear passivated contact showed 682mV i-Voc.

• 한국자기학회지
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• 제15권4호
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• pp.231-235
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• 2005

Al에 Zr과 Nb 또는 Zr과 Ti을 첨가한 삼원계 산화층을 절연층으로 사용한 자기터널접합(Magnetic Tunnel Junction, MTJ)에서, 각 원소의 비율에 따른 자기적 특성과 절연층의 미세구조 특성을 연구하였다. $(ZrNb)_{0.1}Al_{0.9}$ 및 $(ZrTi)_{0.1}Al_{0.9}$ 삼원계 산화 절연층을 가진 자기터널접합의 자기저항비는 Nb, 또는 Ti과 Zr의 첨가 비율이 1 : 1에 가까워질수록 낮아졌으며, Zr과 비교해 Nb 또는 Ti의 첨가량이 많아질수록 자기터널접합의 저항이 감소하였다. 이는 ZrNbAl, ZrTiAl 삼원계 합금 박막은 비정질인 ZrAl 이원계 합금박막과는 달리 다결정체로서 불균일한 산화 절연층을 형성하여 자기저항 및 전기적 특성을 감소시키는 역할을 하기 때문이다. 그러나 삼원계 산화 절연층의 경우 이원계 경우보다 낮은 터널 저항을 특성을 나타내었으며 이는 Nb 또는 Ti이 벤드갭 내에 국부적 에너지 준위를 만들어 에너지 장벽이 감소된 효과로 추측된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.344-344
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• 2010

A capacitor with engineered tunnel barrier composed of High-k materials has been fabricated. Variable oxide thickness (VARIOT) barrier consisting of thin SiO2/HfO2/Al2O3 (2/1/3 nm) dielectric layers were used as engineered tunneling barrier. We studied the electrical characteristics of multi stacked tunnel layers for various RTA (Rapid Thermal Anneal) and FGA (Forming Gas Anneal) temperature.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2003년도 somma/kms meeting
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• pp.93-93
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• 2003

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2004년도 동계학술연구발표회 논문개요집
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• pp.131-132
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• 2004

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2007년도 The 1st International Symposium on Advanced Magnetic Materials
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• pp.263.2-263.2
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• 2007

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2000년도 International Symposium on Magnetics The 2000 Fall Conference
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• pp.317-318
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• 2000

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.139-145
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• 2014

Control of threshold voltage ($V_T$) by ground-plane (GP) technique for planar tunnel field-effect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For $V_T$-modulation larger than 100 mV, heavy ground doping over $1{\times}10^{20}cm^{-3}$ or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common $V_T$-control scheme when these devices are co-integrated.

• Transactions on Electrical and Electronic Materials
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• 제4권6호
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• pp.32-37
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• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.