• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.87-92
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• 2010

The design of avionic embedded systems requires high-dependability. In this paper, we studied the dependability of the triple modular redundancy (TMR) hardware for highly reliable aviation embedded system. In order to evaluate the dependability of the base ARM processor and the TMR ARM processor, we developed the simulation model of the reduced ARM and TMR ARM processors and performed the simulation fault injection for the analysis of the dependability of the two targets. In the fault injection experiments, we calculated the error recovery rate of the two the processor models. From the experimental results, we could confirm that the reliability of the TMR ARM processor was greater than the single ARM processor by ten times in some cases.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.8
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• pp.1440-1446
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• 2008

In this paper, a novel TMR (Triple Modular Redundancy) memory structure is proposed using state feedback control of asynchronous sequential machines. The main ability of the proposed structure is to correct the fault of SEU (Single Event Upset) asynchronously without resorting to the global synchronous clock. A state-feedback controller is combined with the TMR realized as a closed-loop asynchronous machine and corrective behavior is operated whenever an unauthorized state transition is observed so as to recover the failed state of the asynchronous machine to the original one. As a case study, an asynchronous machine modelling of TMR and the detailed procedure of controller construction are presented. A simulation results using VHDL shows the validity of the proposed scheme.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.8
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• pp.748-754
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• 2004

In this paper, we propose the Triple Modular Redundancy (TMR) control system equipped with a checkpoint strategy. In this system, faults in a single processor are masked and faults in two or more processors are detected at each checkpoint time. When faults are detected, the rollback recovery is activated to recover from faults. The conventional TMR control system cannot overcome faults in two or more processors. The proposed system can effectively cope with correlated and independent faults in two or more processors. We develop a reliability model for this TMR control system under correlated and independent transient faults, and derive the reliability equation. Then we investigate the number of checkpoints that maximizes the reliability.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.3
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• pp.527-534
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• 2023

Triple modular redundancy (TMR) systems can continue their mission by virtue of their structural redundancy even if one processor is attacked by faults. In this paper, we propose a new fault tolerance strategy by introducing checkpoints into the TMR system in which data saving and fault detection processes are separated while they corporate together in the conventional checkpoints. Faults in one processor are tolerated by synchronizing the state of three processors upon detecting faults. Simultaneous faults occurring to more than one processor are tolerated by re-executing the task from the latest checkpoint. We propose the checkpoint placement and fault detection strategy to maximize the probability of successful execution of a task within the given deadline. We develop the Markov chain model for the TMR system having the proposed checkpoint strategy, and derive the optimal fault detection and checkpoint interval.

• Proceedings of the KIEE Conference
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• 1985.07a
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• pp.231-233
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• 1985

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2012.05a
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• pp.468-471
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• 2012

This paper describes a construction scheme of hot backup or triple modular redundancy control system in a ground hot-firing test facility to carry out performance assessment of propulsion system used in a space launch vehicle. It was possible for a hot backup redundancy control system with manual operated console to simulate TMR control system. A console layout of control system in control center to restrict imprudent works of operators was proposed.

• Journal of Applied Reliability
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• v.1 no.1
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• pp.9-15
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• 2001

This paper modelled the fail-safe control logic through the frequency coding input and designed the 3-out of-6 self checker using the error detect coding method of information redundancy. In addition, this paper also peformed the reliability parallel numeric analysis regarding single module between fail-safe. control logic module and TMR(Triple Modular Redundancy), therefore, we achieved the result that the fail-safe control logic increases a functional reliability because of decreasing system waste cost and functional overhead rather than the existing hardware redundancy method.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.12
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• pp.1174-1180
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• 2011

Field Programmable Gate Array(FPGA)s are replacing traditional integrated circuits for space applications due to their lower development cost as well as reconfigurability. However, they are very sensitive to single event upset (SEU) caused by space radiation environment. In order to mitigate the SEU, on-board computer of STSAT-3 employed a triple modular redundancy(TMR) and scrubbing scheme. Experimental results showed that upset threshold energy was improved from 10.6 MeV to 20.3 MeV when the TMR and the scrubbing were applied to the on-board computer. Combining the experimental results with the orbit simulation results, calculated bit-flip rate of on-board computer is 1.23 bit-flips/day assuming in the worst case of STSAT-3 orbit.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.6-8
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• 2000

결함허용 시스템은 다양한 형태의 중복을 사용하여 신뢰도를 향상시킬 수 있는 반면, 시스템의 비용을 크게 증가시킨다. 본 논문은 만족스러운 신뢰도를 갖추면서 추가 비용을 적게 요구하는 결함허용 컴퓨터 시스템의 구조를 결정하기 위한 설계 문제를 정의하고 탐색에 기반을 둔 해결법을 제안한다. 이 때, 탐색 기법이 방문하는 탐색 공간의 크기를 줄이기 위하여 사용되는 세 가지의 유용한 사실을 설명한다. 이를 바탕으로 삼중 모듈 중복(TMR: Triple-Modular-Redundancy), 백업 예비(backup sparing), 그리고 혼합 중복(hybride redundancy) 기법과 같은 결함허용 기법들이 시스템 구조에 적용되었을 때, 탐색 공간을 줄이는 용도로 사용될 수 있는 신뢰도 제약조건을 유도해낸다.

• Proceedings of the Korean Reliability Society Conference
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• 2000.04a
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• pp.247-253
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• 2000

본 논문은 정보 여분(Information Redundancy)에서의 에러 검출 코딩(Error Detect Coding) 기법을 이용하여 3-out-of-6 자체 검사기를 설계하고, 주기적인 코드(Frequency Coding) 주입을 통해 고장-안전 제어 논리를 모델링 했다. 고장-안전 제어 논리 모듈과 TMR(Triple Modular Redundancy)의 단일 모듈간에 대해서 신뢰성 병렬 수치 해석을 수행하였고, 이때 고장-안전 제어 논리가 기존의 하드웨어 여분 기법보다 시스템 소모비용과 기능적 오버헤드가 감소되어 기능신뢰성이 증가되는 결과를 얻었다.