• Proceedings of the Materials Research Society of Korea Conference
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• 2006.05a
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• pp.17.1-17.1
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• 2006

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.1-6
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• 2011

We have developed the process of forming one body S-type cantilever probe in the recessed trench for fine-pitched MEMS probe card. The probe (cantilever beam and pyramid tip) was formed using Deep RIE etching and wet etching. The pyramid tip was formed by the wet etching using KOH and TMAH. The process of forming the curved probe was also developed by the wet etching. Therefore, the fabricated probe is applicable for the probe card for DRAM, Flash memory and RF devices tests and probe tip for IC test socket.

• Journal of Powder Materials
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• v.24 no.6
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• pp.464-471
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• 2017

A metal mesh TCE film is fabricated using a series of processes such as UV imprinting of a transparent trench pattern (with a width of $2-5{\mu}m$) onto a PET film, filling it with silver paste, wiping of the surface, and heat-curing the silver paste. In this work nanosized (40-50 nm) silver particles are synthesized and mixed with submicron (250-300 nm)-sized silver particles to prepare silver paste for the fabrication of metal mesh-type TCE films. The filling of these silver pastes into the patterned trench layer is examined using a specially designed filling machine and the rheological testing of the silver pastes. The wiping of the trench layer surface to remove any residual silver paste or particles is tested with various mixture solvents, and ethyl cellosolve acetate (ECA):DI water = 90:10 wt% is found to give the best result. The silver paste with 40-50 nm Ag:250-300 nm Ag in a 10:90 wt% mixture gives the highest electrical conductance. The metal mesh TCE film obtained with this silver paste in an optimized process exhibits a light transmittance of 90.4% and haze at 1.2%, which is suitable for TSP application.

• Journal of IKEEE
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• v.21 no.1
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• pp.1-6
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• 2017

IGBT (Insulated Gate Bipolar Transistor) device is a device with excellent current conducting capability, it is widely used as a switching device power supplies, converters, solar inverter, household appliances or the like, designed to handle the large power. This research was proposed 1200 class dual gate IGBT for electrical vehicle. To compare the electrical characteristics, The planar gate IGBT and trench gate IGBT was designd with same design and process parameters. And we carried to compare electrical characteristics about three devices. As a result of analyzing electrical characteristics, The on state voltage drop charateristics of dual gate IGBT was superior to those of planar IGBT and trench IGBT. Therefore, Aspect to Energy Loss, dual gate IGBT was efficiency. The breakdown volgate and threshold voltage of planar, trench and dual gate IGBT were 1460V and 4V.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.106.1-106
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• 1998

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.443-444
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• 2002

The uniformity of field oxide is critical to isolation property of device in STI, so the control of field oxide thickness in STI-CMP becomes enormously important. The loss of field oxide in shallow trench isolation comes mainly from dishing and erosion in STI-CMP. In this paper, the effect of slurries on the dishing was investigated with both blanket and patterned wafers were selected to measure the removal rate, selectivity and dishing amount. Dishing was a strong function of pattern spacing and types of slurries. Dishing was significantly decreased with decreasing pattern spacing for both slurries. Significantly lower dishing with ceria based slurry than with silica based slurry were achieved when narrow pattern spacing were used. Possible dishing mechanism with two different slurries were discussed based on the observed experimental results.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.629-632
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• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.977-982
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• 2000

Conventional transistors which have vertical structure show increased parasitic capacitance characteristics in accordance with the increase of non-active base area and collector area. These consequently have disadvantage for high speed switching performance. In this paper, a lateral structure transistor which has minimized parasitic capacitance by using SDB(Silicon Direct Bonding) wafer and oxide sidewall isolation utilizing silicon trench technology is presented. Its structural characteristics are designed by ATHENA(SUPREM4), the process simulator from SILVACO International, and its performance is proven by ATLAS, the device simulator from SILVACO International. The performance of the proposed lateral structure transistor is certified through the V$\_$CE/-I$\_$C/ characteristics curve, h$\_$FE/-I$\_$C/ characteristics, and GP-plot. Cutoff Frequency is 13.7㎓.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.3-6
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• 2004

Power semiconductor devices are being compact, high performance and intelligent thanks to recent remarkable developments of silicon design, process and related packaging technologies. Developments of MOS-gate transistors such as MOSFET and IGBT are dominant thanks to their advantages on high speed operation. In conjunction with package technology, silicon technologies such as trench, charge balance and NPT will support future power semiconductors. In addition, wide band gap material such as SiC and GaN are being studies for next generation power semiconductor devices.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.339-341
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• 1997

From this first studies, We have investigated the latch-up characteristics of various CMOS well structures possible with high energy ion implantation processes. In this study, we also investigated those of STI(Shallow Trench Isolation} structures with varing n+/p+ spacing and the depth of trench. STI structure is formed by T-SUPREM4 process simulator, and then latch-up simulations for each case were performed by MEDICI device simulator for latch-up immunity improvement. STI is very effective to preventing the degradation of latch-up characteristics as the n+/p+ spacing is reduced. These studies will allow us to evaluate each technology and suggest guidelines for the optimization of latch-up susceptibility.