• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.67-70
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• 2003

In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

• 전기전자학회논문지
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• 제17권3호
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• pp.365-370
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• 2013

Power MOSFET is developed in power savings, high efficiency, small size, high reliability, fast switching, and low noise. Power MOSFET can be used in high-speed switching transistors devices. Recently attention given to the motor and the application of various technologies. Power MOSFET is a voltage-driven approach switching device and designed to handle on large power, power supplies, converters, motor controllers. In this paper, the 400 V Planar type, and the trench type for realization of low on-resistance are designed. Trench Gate Power MOSFET Vth : 3.25 V BV : 484 V Ron : 0.0395 Ohm has been optimized.

• 한국전기전자재료학회논문지
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• 제27권8호
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• pp.501-504
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• 2014

This paper was developed and described core-process to implement low on resistance which was the most important characteristics of SJ (super junction) MOSFET. Firstly, using process-simulation, SJ MOSFET optimal structure was set and developed its process flow chart by repeated simulation. Following process flow, gate level process was performed. And source and drain level process was similar to genral planar MOSFET, so the process was the same as the general planar MOSFET. And then to develop deep trench process which was main process of the whole process, after finishing photo mask process, we developed deep trench process. We expected that developed process was necessary to develop SJ MOSFET for automobile semiconductor.

• Transactions on Electrical and Electronic Materials
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• 제18권4호
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• pp.195-198
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• 2017

This research analyzed the electrical characteristics of an 80 V optimal trench power MOSFET (metal oxide field effect transistor) for mobile applications. The power MOSFET is a fast switching device in fields with low voltage(<100 V) such as mobile application. Moreover, the power MOSFET is a major carrier device that is not minor carrier accumulation when the device is turned off. We performed process and device simulation using TCAD tools such as MEDICI and TSUPREM. The electrical characteristics of the proposed trench gate power MOSFET such as breakdown voltage and on resistance were compared with those of the conventional power MOSFET. Consequently, we obtained breakdown voltage of 100 V and low on resistance of $130m{\Omega}$. The proposed power MOSFET will be used as a switch in batteries of mobile phones and note books.

• 한국정보통신학회논문지
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• 제10권12호
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• pp.2258-2263
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• 2006

본 논문은 shallow trench isolation (STI) 공정에서 ILD (inter-layer dielectric) 막의 수분에 의해 야기되는 단 채널 (short-channel) nMOSFET의 hump 특성의 원인을 분석하고 억제 방법을 제안하였다. 다양한 게이트를 가지는 소자와 TDS-APIMS(Thermal Desorption System-Atmospheric Pressure Ionization Mass Spectrometry) 측정을 이용하여 hump 특성을 체계적으로 분석하였고, 분석을 바탕으로 단 채널 hump모델을 제안하였다. 제안된 모델에 의한 단 채널 nMOSFET의 hump 현상은 poly-Si 게이트 위의 ILD 막의 수분이 상부의 SiN 막에 의해 밖으로 확산되지 못하고 게이트와 STI의 경계면으로 확산하여 발생한 것이 며, 이를 개선하기 위해 상부의 SiN 막의 증착 전 열공정을 통해 ILD 막의 수분을 효과적으로 배출시킴으로써 hump 특성을 성공적으로 억제하였다.

• ETRI Journal
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• 제35권4호
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• pp.632-637
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• 2013

In this paper, we propose a superjunction trench gate MOSFET (SJ TGMOSFET) fabricated through a simple p-pillar forming process using deep trench and boron silicate glass doping process technology to reduce the process complexity. Throughout the various boron doping experiments, as well as the process simulations, we optimize the process conditions related with the p-pillar depth, lateral boron doping concentration, and diffusion temperature. Compared with a conventional TGMOSFET, the potential of the SJ TGMOSFET is more uniformly distributed and widely spread in the bulk region of the n-drift layer due to the trenched p-pillar. The measured breakdown voltage of the SJ TGMOSFET is at least 28% more than that of a conventional device.

• 전기학회논문지
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• 제58권7호
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• pp.1363-1374
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• 2009

This paper reviews the characteristics and technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The silicon bipolar power transistor has been displaced by silicon power MOSFET's in low and high voltage system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• 전기전자학회논문지
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• 제19권1호
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• pp.110-117
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• 2015

In this paper, a novel trench power MOSFET using a Separate-W-gated technique MOSFET (SWFET) is proposed. Because the SWFET has a very low $Q_{GD}$ compared to other forms of technology, it can be applied to high-speed power systems. The results found that the SWFET-applied $Q_{GD}$ was decreased by 40% when compared to simply using the more conventional trench gate MOSFET. $C_{ISS}$ (input capacitance : $C_{GS}+C_{GD}$), $C_{OSS}$ (output capacitance : $C_{GD}+C_{DS}$) and $C_{RSS}$ (reverse recovery capacitance : $C_{GD}$) were improved by 24%, 40%, and 50%, respectively. The switching characteristics of the inverter circuit shows a 24.9% enhancement of reverse recovery time, and the power efficiency of the DC-DC buck converter increased by 14.2%. In addition, the proposed SWFET does not require additional process steps and There was no degradation in the electrical performance of the current-voltage and on-resistance.

• 한국전기전자재료학회논문지
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• 제17권3호
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• pp.259-266
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• 2004

In this paper. a new two types of EST(Emitter Switched Thyristor) structures are proposed to improve the electrical characteristics including the current saturation capability. Besides, the two dimensional numerical simulations were carried out using MEDICI to verify the validity of the device and examine the electrical characteristics. First, a vortical trench electrode EST device is proposed to improve snap-back effect and its blocking voltage. Second, a dual trench gate EST device is proposed to obtain high voltage current saturation characteristics and high blocking voltage and to eliminate snap-back effect. The two proposed devices have superior electrical characteristics when compared to conventional devices. In the vertical trench electrode EST, the snap-back effect is considerably improved by using the vertical trench gate and cathode electrode and the blocking voltage is one times better than that of the conventional EST. And in the dual trench gate EST, the snap-back effect is completely removed by using the series turn-on and turn-off MOSFET and the blocking voltage is one times better than that of the conventional EST. Especially current saturation capability is three times better than that of the other EST.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.392-395
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• 2003

For the first time, the new dual trench gate Emitter Switched Thyristor is proposed for eliminating snap-back effect which leads to a lot of serious problems of device applications. Also, the parasitic thyristor that is inherent in the conventional EST is completely eliminated in the proposed EST structure, allowing higher maximum controllable current densities for ESTs. Moreover, the new dual trench gate allows homogenous current distribution throughout device and preserves the unique feature of the gate controlled current saturation of the thyristor current. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and $354/{\S}^2$, respectively. But the proposed EST exhibits snap-back with the anode voltage and current density 0.93V and $58A/{\S}^2$, respectively. Saturation current density of the proposed EST at anode voltage 6.11V is $3797A/{\S}^2$. The characteristics of 700V forward blocking of the proposed EST obtained from two dimensional numerical simulations (MEDICI) is described and compared with that of the conventional EST.