• Journal of Information Display
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• v.2 no.2
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• pp.27-31
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• 2001

Transistor slicing refers to the use of multiple smaller transistors in implementing a large MOS transistor. What is special about transistor slicing is that it can reduce the effects of device non-uniformity introduced during the fabrication process. The paper presents the idea of transistor slicing and analyzes the benefits of using transistor slicing in the context of Poly-Si TFT-LCD driving.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.3
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• pp.167-171
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• 2014

This paper examines the destruction behavior of NPN BJT (bipolar junction transistor) by repetition pulse. The injected pulse has a rise time of 1 ns and the maximum peak voltage of 2 kV. Pulse was injected into the base of transistor. Transistor was destroyed, current flows even when the base power is turned off. Cause the destruction of the transistor is damaged by heat. Breakdown voltage of the transistor is 975 V at single pulse, and repetition pulse is 525~575 V. Pulse repetition rate increases, the DT (destruction threshold) is reduced. Pulse Repetition rate is high, level of transistor destruction is more serious.

• Journal of Multimedia Information System
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• v.8 no.2
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• pp.143-146
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• 2021

This work presents an automated transistor biasing scheme for analog integrated circuits. In order to effectively bias the transistor at a desired operating point, the proposed method uses a linearized transistor circuit model along with the curve fitted expressions obtained from the pre-simulated I-V characteristics of the actual transistor. As a result, the transistor size that leads to the desired operating point can be easily determined without heavily relying on the circuit simulator, which will lead to significant design time reduction. Furthermore, the proposed method is applied to an actual amplifier circuit where the design time based on the proposed biasing method showed 10× faster than the conventional design approach using the circuit simulator.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.1-6
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• 2016

In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.261-264
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• 1999

This paper presents a circuit-level method to deal with transistor nonuniformity In this method, which is called transistor slicing, a transistor is implemented as a parallel connection of multiple smaller transistors. The paper analyzes the method and demonstrates that transistor slicing can effectively reduce the nonuniformity in TFT mobility and threshold voltage. The method is particularly useful in Implementing analog functions using poly-silicon TFTs which show a significant level of nonuniformity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.415-419
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• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.218-221
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• 2008

Bottom-gate microcrystalline silicon thin film transistors (${\mu}c$-Si:H TFTs) were fabricated on glass and transparent polyimide substrates by conventional 13.56 MHz RF plasma enhanced chemical vapor deposition at $200^{\circ}C$. The deposition rate of the ${\mu}c$-Si:H film is 24 nm/min and the amorphous incubation layer near the ${\mu}c$-Si:H/silicon nitride interface is unobvious. The threshold voltage of ${\mu}c$-Si:H TFTs can be improved by $H_2$ or $NH_3$ plasma pretreatment silicon nitride film.

• 전기의세계
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• v.11
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• pp.8-13
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• 1963

Solid state nuclear radiation detector에 사용되는 transistor에 의한 저잡음 charge sensitive preamplifier의 설계방식과 이에 대한 실측결과에 관하여 기술하였다. 먼저 transistor noise의 제원인을 분석하고 이 잡음들을 최소로 하기 위하여 이에 관련된 각 parameter에 대하여 이론 및 실험적으로 고찰하였다. 지금까지 알려진 진공관식 증폭기의 최소잡음은 등가전자수로 표시하면 약 250전자 정도이고 그 transistor증폭기에 있어서는 약 1,000전자 정도이었으나 본 설계방식에 의하여 제작된 transistor증폭기에서는 detector를 포함한 전 input capacitance가 약 100PF일때 약 400전자의 양호한 저잡음특성을 보이고 있으며 linearity 및 stability도 매우 좋은 결과를 보이고 있다. 여기에 사용된 cascode회로 자체는 이미 오래 전부터 알려져 있었지만 잡음을 최소로 하기 위한 설계방법은 지금껏 알려지지 않고 있으므로 본 논문에서는 전치증복기의 소요이득에서 잡음을 최소로 할 수 있는 설계방식을 확립하여 이 방식에 의한 실측결과는 종래의 transistor를 사용한 것보다 가장 좋았다.

• International journal of advanced smart convergence
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• v.1 no.1
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• pp.61-64
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• 2012

The ultraviolet and visible light responsive properties of the amorphous indium gallium zinc oxide thin film transistor have been investigated. Amorphous indium gallium zinc oxide (a-IGZO) thin film transistor operate in the enhancement mode with saturation mobility of $6.99cm^2/Vs$, threshold voltage of 13.5 V, subthreshold slope of 1.58 V/dec and an on/off current ratio of $2.45{\times}10^8$. The transistor was subsequently characterized in respect of visible light and UV illuminations in order to investigate its potential for possible use as a detector. The performance of the transistor is indicates a high-photosensitivity in the off-state with a ratio of photocurrent to dark current of $5.74{\times}10^2$. The obtained results reveal that the amorphous indium gallium zinc oxide thin film transistor can be used to fabricate UV photodetector operating in the 366 nm.