• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.7
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• pp.47-59
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• 1993

The thermal stability of "stuffed" TiN/Ti barrier matals with different annealing history has been studied to improve the contact reliability of Al/Si contacts in 16M DRAM. The annealing conditions before the Al deposition such as film thickness, the annealing temperature and the annealing ambient have been varied. For TiN(900A)/Ti(300A) annealed at 450 in nitrogen ambient to form a "stuffed barrier" by inducing oxygen atoms into grain boundaries, there is no observation of Al penetrations into Si substrates after the post heat treatment of up to 700 even though there are massive amounts of Al found in TiN film after the post heat treatment of 600 indicating that TiN has a "sponge-like" function due to its ability to absorb several amounts of aluminum at elevated temperature. The TiN/Ti diffusion barrier annealed at 550 has, however, failed after the post heat treatment at 600. The thinner diffusion barriers with TiN(300A)/Ti(100A) failed after the post heat treatment at 600.he post heat treatment at 600.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.54-56
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• 2001

The $SiH_4$ soak step is widely used during the CVD Tungsten(W) plug deposition process on the Ti/TiN barrier metal to prevent the $WF_6$ attack to the underlayer metal. We tried to reduce or skip the time of $SiH_4$ soak process to optimize W-plug deposition process on Via. The electrical characteristics including Via resistance and the structure of W film are affected according to $SiH_4$ soak time. The elimination possibility of $SiH_4$ soak process was confirmed in the case of that the CVD W film grows on the stable Ti/TiN underlayer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.179-180
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• 2007

반도체의 최소 회로 선폭이 감소함에 따라 Contact 저항이 크게 증가하게 된다. Contact 저항을 낮추기 위하여 Tungsten Metal Contact을 일반적으로 사용하며, Si 기판과의 Ohmic 접촉 및 WF6의 Fluorine과 Si 반응을 억제하기 위한 Barrier Metal로 Ti/TiN 이중막을 사용한다. 본 논문에서는 90nm급 이하 제품의 CVD Ti/TiN Barrier Metal이 유발하는 불량 현상과 원인 규명에 대하여 연구하였으며, Ohmic Contact형성을 위해 TiSix형성 최적화 방안에 대해 정리하였다.

• Electrical & Electronic Materials
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• v.8 no.1
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• pp.56-63
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• 1995

MESFETs of the Ti/Au and Ti/Pd/Au gate were fabricated on n-type GaAs. Interdiffusion at Schottky interfaces, Schottky contact properties, and MESFET characteristics with heat treatment were investigated. Ti of Ti/Au contact and Pd of Ti/Pd/Au contact acted as a barrier metal against interdiffusion of Au at >$220^{\circ}C$. Pd of Ti/Pd/Au contact acted as a barrier metal even at >$360^{\circ}C$, however, Ti of Ti/Au contact promoted interdiffusion of Au instead of role of barrier metal. As the heat treatment temperature increases, in the case of both contact, saturated drain current and pinch off voltage decreased, open channel resistance increased, and degree of parameter variation in Ti/Au gate was higher than in Ti/Pd/Au gate at >$360^{\circ}C$ Schottky barrier height of Ti/Au and Ti/Pd/Au contacts was 0.69eV and 0.68eV in the as-deposited state, respectively, and Fermi level was pinned in the vicinity of 1/2Eg. As the heat treatment temperature increases, barrier height of Ti/Pd/Au contact increased, however, decreased at >$360^{\circ}C$ in the case of Ti/Au contact. Ideality factor of Ti/Au contact was nearly constant regardless of heat treatment, however, increased at >$360^{\circ}C$ in the case of Ti/Au contact. From the results above, Ti/Pd/Au was stable gate metal than Ti/Au.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.94-100
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• 1994

The junction failure mechanism of W plugs has not been fully understood while the selective W deposition has been widely used for plugging interconnection lines. In this paper, the thermal stability and junction failure mechanism of sub-micron contacts using selective CVD-W plugs were intensively studied with the metal lines of AISiCu, Ti/AISiCu and TiN/AISiCu. The experimental results showed that the contact chain resistance and leakage current in the AISiCu and Ti/AISiCu metallizations were significantly degraded after annealing. From the SEM analysis, it was found that the junction spiking, due to the Al atoms diffusion along the porous interface between selective CVD-W and contactside wall, caused the junction failure. In constast, there was no degradation of the contact resistance and junction leakage current in TiN/AISiCu metal structu-re. It is believed that the TiN barrier layer could prevent AI(Ti) atoms Fromdiffusing. Therefore, TiN barrier between W plug and Al should be used to impro-ve the thermal stability of sub-micron contacts using the selective CVD-W plugs.

• Proceedings of the Materials Research Society of Korea Conference
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• 1997.10a
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• pp.147-147
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• 1997

• Proceedings of the Korean Vacuum Society Conference
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• 1999.02a
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• pp.105-105
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• 1999

• Korean Journal of Materials Research
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• v.10 no.1
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• pp.90-96
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• 2000

The effects of the type and thickness of underlayers on the crystallographic texture and the sheet resistance of aluminum thin films were studied. Sputtered Ti and Ti/TiN were examined as the underlayer of the aluminum films. The texture and the sheet resistance of the metal thin film stacks were investigated at various thicknesses of Ti or TiN, and the sheet resistance was measured after annealing at $400^{\circ}C$ in an nitrogen ambient. For the Ti underlayer, the minimum thickness to obtain excellent texture of aluminum <111> was 10nm, and the sheet resistance of the metal stack was greatly increased after annealing due to the interdiffusion and reaction of Al and Ti. TiN between Ti and Al could suppress the Al-Ti reaction, while it deteriorated the texture of the aluminum film. For the Ti/TiN underlayer, the minimum Ti thickness to obtain excellent texture of aluminum <111> was 20nm, and the minimum thickness of TiN to function as a diffusion barrier between Ti and Al was 20nm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.1
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• pp.1-12
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• 2003

This paper describes a study on the abnormal behavior of the electrical characteristics of the (n)GaAs/Ti/Pt/Au Schottky contacts prepared by the two techniques of electron beam deposition and rf sputtering and after an annealing treatment. The samples were characterized by I-V and C-V measurements carried out over the temperature range of 150 - 350 K both in the as prepared state and after a 300 C, 30 min. anneal step. The variation of ideality factor with forward bias, the variation of ideality factor and barrier height with temperature and the difference between the capacitance barrier and current barrier show the presence of a thin interfacial oxide layer along with barrier height inhomogenieties at the metal/semiconductor interface. This barrier height inhomogeneity model also explains the lower barrier height for the sputtered samples to be due to the presence of low barrier height patches produced because of high plasma energy. After the annealing step the contacts prepared by electron beam have the highest typical current barrier height of 0.85 eV and capacitance barrier height of 0.86 eV whereas those prepared by sputtering (at the highest power studied) have the lowest typical current barrier height of 0.67 eV and capacitance barrier height of 0.78 eV.

• Journal of the Korean Vacuum Society
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• v.9 no.2
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• pp.162-166
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• 2000

High quality $Si_3N_4$ metal-insulator-metal (MIM) capacitors were realized by plasma enhanced chemical vapor deposition (PECVD). Titanium nitride (TiN) adapted as a diffusion barrier reduced the interfacial reaction between $Si_3N_4$ dielectric layer and aluminum metal electrode showing neither hillock nor observable precipitate along the interface. The capacitance and the current-voltage characteristics of the MIM capacitors showed that the minimum thickness of $Si_3N_4$ layer should be limited to 500 $\AA$ under the present process, below which most of the capacitors were electrically shorted resulting in the devastation of on-wafer yield. According to the transmission electron microscopy (TEM) on the cross-sectional microstructure of the capacitors, the dielectric breakdown was caused by slit-like voids formed at the interface between TiN and $Si_3N_4$ layers when the thickness of $Si_3N_4$ layer was less than 500 $\AA$. Based on the calculation of thermally-induced residual stress, the formation of voids was understood from the mechanistic point of view.