• 전기의세계
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• 제23권6호
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• pp.49-55
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• 1974

Amorphous semiconductor from As 30 Te 48 Ge 10 Si 12 was prepared, and studied electron microscopy, X-ray analysis and resistivity measurement. It's resistivity is 1.56*10$^{6}$ .ohm.-cm when small ampule is used for preparing sample it is found that no phase separation has occurced by electron microscopy, and that phase transition temperature is 232.deg. C by differential Thermal Analysis. The specimen showed threshold switching that the low resistance state occur at critical electric field and the resistance recover at low applied field. Critical electric field of the switching is 10$^{5}$ V/cm at room temperature. Threshold voltage secreace exponentially with increasing ambient temperature and at that each voltage resistance of the switching device increase exponentially. According to the series resistance and applied vottage current slope on the V-I curve is varied. When applied voltage is decreased after switching, the resistance of the switching device is increased. By this result the origin of the switching is the Joule's heating.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2007년도 춘계학술대회
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• pp.221-225
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• 2007

We have prepared $\delta$-phase SbTe alloy with various Sb contents of 64, 72, and 76 at. % and investigated the phase change temperature, the crystal structures of $\delta$-phase SbTe alloy, and determined the ovonic threshold switching voltages with edge contact type phase transition dimensions. As a result, the crystallization temperature is slightly reduced from 126 to $122^{\circ}C$, whereas the melting temperature is not changed. The ovonic threshold switching voltage is reduced from 1.6 to 0.9 V as increasing the Sb content from 64 to 76 at. %. It is found that the reductions of crystallization temperature and the ovonic threshold switching voltage are closely related with the interplanar spacing between adjacent atomic layers and the stacking number of atomic layers in a unit cell.

• 대한전기학회논문지
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• 제44권7호
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• pp.901-907
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• 1995

The switching characteristics of As$_{10}$ Ge$_{15}$ Te$_{75}$ thin film were investigated under d.c. bias. And the frequency dependence of the conductivity was analysed with regard to the temperature dependence, in order to find the physical properties of the As$_{10}$ Ge$_{15}$ Te$_{75}$ thin film ; a characteristic relaxation time (.tau.$_{0}$ ), the spatial density of defect states (N), and the localized wavefunction (.alpha.$^{-1}$ ). It was formed that the threshold voltage depends on thickness, electrode distance, annealing time and temperature, respectively. The threshold voltage is increased as the thickness and the electrode distance is increased, while the threshold voltage is decreased in proportion to the increased annealing time and temperature.

• 한국안광학회지
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• 제2권1호
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• pp.1-8
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• 1997

강탄성 구역 $S_k$ 상태에서 $S_p$ 상태로 스윗청 될 때 ${\beta}-Tb_2(MoO_4)_3$, 단결정의 자발변형텐서 값으로부터 격자점의 상대적 변위를 계산할 수 있는 공식을 유도하였다. 엔탈피의 보존법칙을 이용하여 특정 방향에 대한 문턱 스윗청력의 측정치를 이용하여 임의의 방향에 대한 문턱 스윗청력을 계산할 수 있는 공식을 유도하였으며, 이 공식에서 유도한 이론치와 (${\theta}=90^{\circ}$, ${\phi}$)가 ($90^{\circ}$, $15^{\circ}$), ($90^{\circ}$, $30^{\circ}$), ($90^{\circ}$, $45^{\circ}$), ($90^{\circ}$, $60^{\circ}$), ($90^{\circ}$, $75^{\circ}$)인 경우에 실측한 측정값은 잘 일치하였다.

• 한국전기전자재료학회논문지
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• 제36권6호
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• pp.547-555
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• 2023

High-density crossbar arrays based on storage class memory (SCM) are ideally suited to handle an exponential increase in data storage and processing as a central hardware unit in the era of AI-based technologies. To achieve this, selector devices are required to be co-integrated with SCM to address the sneak-path current issue that indispensably arises in such crossbar-type architecture. In this perspective, we first summarize the current state of tellurium-based threshold-switching devices and recent advances in the material, processing, and device aspects. We thoroughly review the physicochemical properties of elemental tellurium (Te) and representative binary tellurides, their tailored deposition techniques, and operating mechanisms when implemented in two-terminal threshold switching devices. Lastly, we discuss the promising research direction of Te-based selectors and possible issues that need to be considered in advance.

• Journal of Positioning, Navigation, and Timing
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• 제8권3호
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• pp.95-105
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• 2019

A method that applies space-time adaptive signal processing (STAP) algorithm based on an array antenna consisting of multiple antenna elements has been known to be effective to remove wide-band jamming signals in GPS receivers. However, the occurrence of phase distortion in navigation signals has been a problem when navigation signals, from which jamming signals are removed using STAP, are supplied to global positioning system (GPS) receivers. This paper verified the navigation performance degradation as a result of phase distortion. To mitigate this phenomenon, this paper proposes a mode switching scheme, in which a bypass mode is adopted to make the best use of the tracking performance of receivers without performing signal processing when jamming signals are not present or weak, and a STAP mode is employed when jamming signals exceed the threshold value. In this paper, the mode switching scheme is proposed for two environments: when receivers are stationary, and when receivers are moving. This paper confirmed that the performance of position error improved because phase distortion could be excluded due to STAP if the bypass mode was adopted under a condition where the jamming signal power level was below the threshold value in an environment where receivers were stationary. However, this paper also observed that the navigation failed due to the instability of tracking performance of receivers due to phase distortion that occurred at the switching time, although the number of switching could be reduced dramatically by proposing a dual threshold scheme of on- and off-thresholds that switched a mode due to the array antenna characteristics of varying gains according to the jamming signal incident direction in an environment where receivers were moving. The analysis results verified that running the STAP algorithm at all times is more efficient than the mode switching, in terms of maintaining stable navigation and ensuring position error performance, to remove jamming signals in an environment where receivers were moving.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제13권1호
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• pp.110-132
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• 2019

To ensure reliable and secure communication in heterogeneous cellular network (HCN) with imperfect channel state information (CSI), we proposed a coordinated multipoint (CoMP) transmission scheme based on dual-threshold optimization, in which only base stations (BSs) with good channel conditions are selected for transmission. First, we present a candidate BSs formation policy to increase access efficiency, which provides a candidate region of serving BSs. Then, we design a CoMP networking strategy to select serving BSs from the set of candidate BSs, which degrades the influence of channel estimation errors and guarantees qualities of communication links. Finally, we analyze the performance of the proposed scheme, and present a dual-threshold optimization model to further support the performance. Numerical results are presented to verify our theoretical analysis, which draw a conclusion that the CoMP transmission scheme can ensure reliable and secure communication in dense HCNs with imperfect CSI.

• 한국세라믹학회지
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• 제15권3호
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• pp.135-139
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• 1978

Sintering oxide which was prepared by sintering at $1200^{\circ}C$ the mixture of ${\gamma}$-$Fe_2O_3$ and $Sb_2O_3$ in 2 : 1 mol ratio, showed 1st electrical switching and stable 2nd switching when D.C. voltage was applied. This electrical switching mechanism was known to be thermal mechanism from dependence of environmental temperature of threshold Voltage(Vm), Current(Im) and the conductivity of the current filament of the sintering oxide.

• 전자공학회논문지
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• 제51권8호
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• pp.172-177
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• 2014

두 가지 $N_2$ 프로세스(성장 중 반응성 질소 그리고 질소 플라즈마 경화)에 의해 특별히 개선된 AsGeTeS 위에 만들어진 문턱 스위칭 소자를 제시하고자 한다. 적층과 열적 안정적인 소자 구조가 가능한 두 스텝 프로세스에서의 질소의 사용은 나노급 배열 회로의 응용에서의 스위치와 메모리 소자의 집적을 가능하게 한다. 이것의 좋은 문턱 스위칭 특성에도 불구하고 AsTeGeSi 기반의 스위치는 높은 온도에서의 신뢰성 있는 저항 메모리 적용에 중요한 요소를 가진다. 이것은 보통 Te의 농도 변화에 기인한다. 그러나 chalconitride 스위치(AsTeGeSiN)은 $30{\times}30(nm^2)$ 셀에서 $1.1{\times}10^7A/cm^2$가 넘는 높은 전류 농도를 갖는 높은 온도 안정성을 보여준다. 스위치의 반복 능력은 $10^8$번을 넘어선다. 더하여 AsTeGeSiN 선택 소자를 가진 TaOx 저항성 메모리를 사용한 1 스위치-1저항으로 구성된 메모리 셀을 시연하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 추계학술대회 논문집 학회본부
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• pp.199-201
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• 1994

The switching characteristics of $As_{10}Ge_{15}Te_{75}$ thin film were investigated under dc bias. It was found that the threshold voltage depends on thickness, electrode distance, annealing time and temperature, respectively. The threshold voltage is increased as the thickness and the electrode distance is increased, while the threshold voltage is decreased in proportion to the increased annealing time and temperature.