• 제목/요약/키워드: Thin Film Thickness

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저온 고체산화물연료전지 구현을 위한 다층 나노기공성 금속기판의 제조 (Development of Metal Substrate with Multi-Stage Nano-Hole Array for Low Temperature Solid Oxide Fuel Cell)

  • 강상균;박용일
    • 한국세라믹학회지
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    • 제42권12호
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    • pp.865-871
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    • 2005
  • Submicron thick solid electrolyte membrane is essential to the implementation of low temperature solid oxide fuel cell, and, therefore, development of new electrode structures is necessary for the submicron thick solid electrolyte deposition while providing functions as current collector and fuel transport channel. In this research, a nickel membrane with multi-stage nano hole array has been produced via modified two step replication process. The obtained membrane has practical size of 12mm diameter and $50{\mu}m$ thickness. The multi-stage nature provides 20nm pores on one side and 200nm on the other side. The 20nm side provides catalyst layer and $30\~40\%$ planar porosity was measured. The successful deposition of submicron thick yttria stabilized zirconia membrane on the substrate shows the possibility of achieving a low temperature solid oxide fuel cell.

와전류센서를 이용한 실시간 웨이퍼 박막두께측정 시스템 구현 (Real-time wafer thin-film thickness measurement system implementation with eddy current sensors.)

  • 김남우;허창우
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2013년도 추계학술대회
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    • pp.383-385
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    • 2013
  • 반도체소자의 고속실현을 위해서 알루미늄배선에서 40% 가량 성능을 높이는 반면 제조비용은 30%까지 낮출 수 있는 구리를 선호하고 있으나, 식각이 잘 되지 않아 원하는 패턴으로 만들어 내기가 곤란한 공정기술의 어려움과 구리물질이 지닌 유독성문제를 가지고 있다. 기존의 식각기술로는 구리패턴을 얻을 수 없는 기술적 한계 때문에 화학.기계적 연마(CMP)를 이용한 평탄화와 연마를 통해서 구리배선을 얻는 다마스커스(Damascene)기술이 개발됐고 이를 이용한 구리배선기술이 현실적으로 가능하게 됐다. CMP를 이용한 평탄화 및 연마 공정에서 Wafer에 도포된 구리의 두께를 실시간으로 측정하여 정밀하게 제어할필요가 있는데, 본 논문에서는 와전류를 이용하여 옹고스트롬 단위의 두께를 실시간으로 측정하여 제어 하는 시스템구현에 대해 기술한다.

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Fabrication of gate electrode for OTFT using screen-printing and wet-etching with nano-silver ink

  • Lee, Mi-Young;Song, Chung-Kun
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.889-892
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    • 2009
  • We have developed a practical printing technology for the gate electrode of organic thin film transistors(OTFTs) by combining screen-printing with wet-etching process using nano-silver ink as a conducting material. The screen-printed and wet-etched Ag electrode exhibited a minimum line width of ~5 um, the thickness of ~65 nm, and a resistivity of ${\sim}10^{-6}{\Omega}{\cdot}cm$, producing good geometrical and electrical characteristics for gate electrode. The OTFTs with the screen-printed and wet-etched Ag electrode produced the saturation mobility of $0.13cm^2$/Vs and current on/off ratio of $1.79{\times}10^6$, being comparable to those of OTFT with the thermally evaporated Al gate electrode.

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The Study of Nanocrystalline Silicon Bottom-gate Thin Film Transistor Fabricated at Low Temperature for Flexible Display

  • Lee, Youn-Jin;Lee, Kyoung-Min;Hwang, Jae-Dam;No, Kil-Sun;Yoon, Kap-Soo;Yang, Sung-Hoon;Hong, Wan-Shick
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.557-559
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    • 2009
  • We attempted modulation of hydrogen dilution ratio to achieve both the minimal incubation layer and high deposition rate. The incubation layer thickness was estimated by transmission electron microscopy (TEM) and crystallization fraction was measured by Raman spectroscopy.

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Low Work Function and Sharp Field Emitter Arrays by Transfer Mold Fabrication Method

  • Nakamoto, Masayuki;Sato, Genta;Shiratori, Kohji
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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    • pp.1049-1052
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    • 2007
  • Extremely sharp and uniform Transfer Mold FEAs with thin film low work function TiN emitter material have been fabricated by controlling the thickness of the coated emitter materials to realize high efficient, high reliable and low-cost vacuum nanoelectronic devices..Their tip radii are 8.3-13.8 nm. Turn-on electric fields of the Ni FEAs and TiN-FEAs resulted in the low electric field values of $31.6\;V/{\mu}m$ and $44.2V/{\mu}m$,respectively, at the short emitter/anode distance: less than $30\;{\mu}m$, which are lower than those of conventional FE As such as Spindt type FEAs and carbon nan otube FEAs The Transfer Metal Mold fabrication method is one of the best methods of changing emit ter materials with sharp and uniform emit ter shapes.

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Ni 박막 촉매 Etching 조건에 따른 탄소나노튜브 성장 (Growth of Carbon Nanotubes Depending on Etching Condition of Ni-catalytic Layer)

  • 정성희;장건익;류호진
    • 한국전기전자재료학회논문지
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    • 제14권9호
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    • pp.751-756
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    • 2001
  • Carbon nanotubes(CNTs) was successfully grown on Ni coated silicon wafer substrate by PECVD technique(Plasma Enhanced Chemical Vapor Deposition). As a catalyst, Ni thin film of thickness ranging from 15∼30nm was prepared by electron beam evaporator system. In order to find the find the optimum growth condition, initially two different types of gas mixtures such as C$_2$H$_2$-NH$_3$ and C$_2$H$_2$-NH$_3$-Ar were systematically investigated by adjusting the gas mixing ratio in temperature of 600$^{\circ}C$ under 0.4 torr. The diameter of the grown CNTs was 40∼200nm. The diameter of the CNTs increases with increasing the Ni particles size. TEM images clearly demonstrated synthesized nanotubes to be multiwalled.

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MIS 구조의 DLPC LB 막의 제작과 전압-전류 특성 (Fabrication of DLPC LB films with MIS structure and I-V characteristics)

  • 이우선;정용호;정종상;손경춘;김상용;장의구;이경섭
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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    • pp.155-158
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    • 1998
  • MLS capacitor with lipid ultra thin films were deposited by Langmuir-Blodgett (LB) method on the sillicon wafer. The current versus voltage and capacitance versus voltage relationships are depend on the applied voltage, electrode area and electrode materials. LB films deposited were made of L-$\alpha$-DLPC, the 1 layer's thickness of 35$\AA$ was measured by ellipsometer. And MLS capacitor with different electrode materials, the work function of these materials was investigated to increase the leakage current. The result indicated the lower leakage current and very high saturation value of capacitance was reached within 700-800 pF when the two electrode was Ag. And $\varepsilon$$_1$, $\varepsilon$$_2$ versus photon energy showed good film formation.

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CdS/(P)Si 이종접합 태양전지에 관한연구 (A Study on the Cd S/(p) Si heterojunction Solar Cell)

  • 전춘생;전창식;윤문수;허창수
    • 대한전기학회논문지
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    • 제37권2호
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    • pp.96-101
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    • 1988
  • This work is concerned with the fabrication process and photo-response characteristics of Cd S/(p) Si solar cells. In order to fabricate the cell. low grade Si wafer has been used as an absorber and Cd S which works as a window material has been prepared by vacuum evaporation. Cd S thin film, as evaporated, is polycristal and resistance is very high but these properties are improved by annealing. The properties of the fabricated cells are found to depend largely on the transmittance of Cd S. The effects of Cd S thickness and annealing condition on the fill factor and efficiency of the cell are investigated quantitatively.

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박막 게이트 산화막에 대한 Ru-Zr 금속 게이트의 신뢰성에 관한 연구 (A Study on the Reliability of Ru-Zr Metal Gate with Thin Gate Oxide)

  • 이충근;서현상;홍신남
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제53권4호
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    • pp.208-212
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    • 2004
  • In this paper, the characteristics of co-sputtered Ru-Zr metal alloy as gate electrode of MOS capacitors have been investigated. The atomic compositions of alloy were varied by using the combinations of relative sputtering power of Ru and .Zr. C-V and I-Vcharacteristics of MOS capacitors were measured to find the effective oxide thickness and work function. The alloy made of about 50% of Ru and 50% of Zr exhibited an adequate work function for nMOS. C-V and I-V measurements after 600 and $700^{\circ}C$ rapid thermal annealing were performed to prove the thermal and chemical stability of the Ru-Zr alloy film. Negligible changes in the accumulated capacitance and work function before and after annealing were observed. Sheet resistance of Ru-Zr alloy was lower than that of poly-silicon. It can be concluded that the Ru-Zr alloy can be a possible substitute for the poly-silicon used as a gate of nMOS.

초기변형 최소화를 위한 광변조 압전 다층박막 액추에이터의 설계, 제작 및 실험 (Design Fabrication and Test of Piezoelectric Multi-Layer Cantilever Microactuators for Optical Signal Modulation)

  • 김명진;조영호
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제49권9호
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    • pp.495-501
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    • 2000
  • This paper presents a method to minimize the initial deflection of a multi-layer piezoelectric microactuator without loosing its piezoelectric deflection performance required for light modulating micromirror devices. The multi-layer piezoelectric actuator composed of PZT silicon nitride and platinum layers deflects or buckles due to the gradient of residual stress. Based on the structural analysis results and relationship between process conditions and mechanical properties we have modified the fabrication process and the thickness of thin film layers to reduce the initial residual stress deflection without decreasing its piezoelectric deflection performance. The modified designs fabricated by surface-micromachining process achieved the 77% reduction of the initial deflection compared with that of the conventional method based on the measured micromechanical material properties is applicable to the design refinement of multi-layer MEMS devices and micromechanical structures.

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