• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.162-163
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• 2008

이 논문에서는 Polyimide 기판의 $O_2$ 플라즈마 처리효과에 따른 GZO 박막의 구조적, 전기적, 광학적인 특성을 고찰하였다. ICP-RIE 방법을 이용하여 Polyimide 기판의 $O_2$ 플라즈마 처리의 변수로 RF power와 처리시간을 각 100 ~ 400 W, 120 ~ 600 초까지 조절하였다. RF 스퍼터링 방법으로 $O_2$ 플라즈마 처리효과에 따른 Polyimide 기판을 4인치의 GZO(ZnO : 95 wt%, $Ga_2O_3$ 5 wt%) 타겟을 사용하여 RF power 90 W, 공정압력 5 mTorr, Ar gas 20 sccm, 기판거리 5 cm, 박막두께 500nm, 상온의 조건으로 GZO 박막을 증착 하였다. Polyimide 기판에 $O_2$ 플라즈마 처리를 하지 않고 증착한 GZO 박막의 비저황은 $1.02\times10^{-2}\Omega$-cm 이었고 RF power 100W, 처리시간 120 초로 $O_2$ 플라즈마 처리 후에 증착한 GZO 박막의 비저항이 $1.89\times10^{-3}\Omega$-cm인 최적의 값이 측정되었으며 RF power가 증가할수록 투과도는 감소하였지만 처리시간의 변화에 따라서는 투과도 변화가 거의 없었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.370-370
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• 2008

ITO 박막은 현재 차세대 디스플레이인 LCD, PDP, ELD 등의 평판 디스플레이의 화소전극 및 공통전극으로 가장 많이 적용되고 있는 소재이며, 최근에는 태양전지의 투명전극으로 그 용도가 더욱 증가되고 있다. 이러한 소자들의 투명 전도막으로 사용되기 위해서는 가시광선 영역에서 80% 이상의 높은 투과도와 낮은 면 저항을 가져야 한다. 광 투과도와 면 저항은 ITO 박막의 증착조건에 따라 변하게 되는데 본 연구에서는 DC 마그네트론 스퍼터링법을 이용하여 Indium-Tin Oxide (ITO) 박막을 제작하고, 제작된 ITO 박막의 전기적 특성과 광학적 특성을 측정하여 공정조건에 따른 박막의 특성 변화를 평가하였다. 증착 조건은 주로 기판 온도와 증착 시간을 변화시켰다. 본 실험에서는 $In_2O_3$ : $SnO_2$의 조성비가 9:1 비율의 순도 99.99% ITO 타겟을 사용하였으며, coming 1737 glass를 30$\times$30 mm 크기로 가공하여 기판온도와 증착시간을 변화시키면서 ITO 박막을 제조하였다. 예비실험을 통해 인가전력 50W, 초기 진공 $2\times10^{-6}$ Torr, 작업 진공 $3.5\times10^{-2}$ Torr, 기판과 타겟 사이의 거리를 10 cm로 고정하였다. 기판 온도는 히터를 가열하지 않은 상온 ($25^{\circ}C$)에서 $400^{\circ}C$까지의 범위에서 변화시켰고, 증착시간은 5분에서 30분까지의 범위에서 변화시켰다. 증착된 박막의 면 저항 촉정을 위해 4 point probe를 사용하였고, 홀 (hall) 계수 측정기 (HMS-300)를 이용하여 홀 계수를 측정하였으며, 또한 박막의 두께는 $\alpha$-step을 사용하여 측정하였다. ITO 박막의 상분석을 위해 XRD를 사용 하였고, SEM을 이용하여 미세구조를 관찰하였다. 실험 결과로는 기판온도 $400^{\circ}C$, 증착시간 15분 이상에서는 면 저항이 모두 $8\Omega$/$\Box$이하로 낮게 나왔으며, 투과율 또한 모두 80% 이상의 높은 투과도를 보였다. 또한 ITO박막의 전기 전도도는 캐리어 농도와 이동도의 측정을 통해 두 가지 인자들에 의해 비례되는 것을 확인하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.44-48
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• 2013

Niobium oxide($Nb_2O_5$) films were deposited on p-type Si wafers at room temperature using in-line pulsed-DC magnetron sputtering system with various frequencies. The different duty ratios were obtained by varying the frequency of pulsed DC power from 100 to 300 kHz at the fixed reverse time of $1.5{\mu}s$. From the thickness of the sputtered $NbO_x$ films, it was possible to obtain much higher deposition rate in case of pulsed-DC sputtering than RF sputtering. However, the similar leakage currents and structural characteristics were obtained from the metal-insulator-semiconductor(MIS) structure fabricated with the $NbO_x$ films and the x-ray photoelectron spectroscopy(XPS) results in spite of the different deposition rates. From the experimental results, the $NbO_x$ films sputtered by pulsed-DC sputtering are expected to be used in the fabrication process instead of RF sputtering.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.11
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• pp.816-820
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• 2013

We investigated the characteristics of the silicon oxy-nitride and nitride films grown by plasma-enhanced chemical vapor deposition (PECVD) at the low temperature with a varying $NH_3/N_2O$ mixing ratio and a fixed $SiH_4$ flow rate. The deposition temperature was held at $150^{\circ}C$ which was the temperature compatible with the plastic substrate. The composition and bonding structure of the nitride films were investigated using Fourier transform infrared spectroscopy (FTIR) and X-ray photoelectron spectroscopy (XPS). Nitrogen richness was confirmed with increasing optical band gap and increasing dielectric constant with the higher $NH_3$ fraction. The leakage current density of the nitride films with a high NH3 fraction decreased from $8{\times}10^{-9}$ to $9{\times}10^{-11}(A/cm^2$ at 1.5 MV/cm). This results showed that the films had improved electrical properties and could be acceptable as a gate insulator for thin film transistors by deposited with variable $NH_3/N_2O$ mixing ratio.

• Korean Chemical Engineering Research
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• v.49 no.6
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• pp.781-785
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• 2011

In this work, a nano-sized samaria-doped ceria(SDC) was prepared by a urea-based hydrothermal method and characterized by XRD, FESEM and TEM. It was observed that the increase in synthesis time and temperature gave rise to crystallity and particles size. Moreover, the synthesised powders had a excellent ion-conductivity(0.1 S/cm at 600~$800^{\circ}C$) which is suitable for electrolyte of intermediate temperature-solid oxide fuel cell(IT-SOFC). Subsequently for use as electrolyte for anode-supported IT-SOFC, we tried to deposit the SDC powder on a porous NiO-SDC substrate by electrophoretic deposition(EPD) method. From the FESEM observation, a compact

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.330-332
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• 2009

Highly stable bottom gate thin film transistors(TFTs) with a zinc indium tin oxide(Zn-In-Sn-O:ZITO) channel layer have been fabricated by rf-magnetron co-sputtering using a indium tin oxide(ITO:90/10), a tin oxide and a zinc oxide targets. The ZITO TFT (W/L=$40{\mu}m/20{\mu}m$) has a mobility of 24.6 $cm^2$/V.s, a subthreshold swing of 0.12V/dec., a turn-on voltage of -0.4V and an on/off ratio of >$10^9$. When gate field of $1.8{\times}10^5$ V/cm was applied with source-drain current of $3{\mu}A$ at $60^{\circ}C$, the threshold voltage shift was ~0.18 V after 135 hours. We fabricated AM-OLED driven by highly stable bottom gate Zn-In-Sn-O TFT array.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.3
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• pp.156-161
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• 2014

We have investigated the optical properties of plamonic waveguide with tapered structure based on InP material for photonic integrated circuit(PIC). The proposed plasmonic waveguide is covered with the Ag thin film to generate the plasmonic wave on metallic interface. The optical characteristics of plasmonic waveguide were calculated using the three-dimensional finite-difference time-domain method. The plasmonic waveguide was fabricated with the lengths of 2 to $10{\mu}m$ and the widths of 400 to 700 nm, respectively. The plasmonic mode and optical loss were measured. The optimum plasmonic length is $10{\mu}m$ and widths are 600 and 700 nm in the fabricated waveguide. This plasmonic waveguide can be directly integrated with other conventional optical devices and can be essential building blocks of PIC.

• Transactions on Electrical and Electronic Materials
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• v.10 no.3
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• pp.93-96
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• 2009

The Al-doped ZnO (AZO) films were deposited on a glass substrate by RF magnetron sputtering in pure Ar and $Ar+H_2$ gas ambient at temperature of $100^{\circ}C$ and annealed in hydrogen ambient at the temperature range from 100 to 300 $^{\circ}C$, respectively. It was found that either the addition of hydrogen to the sputtering gas or the annealing treatment effectively reduced the resistivity of the AZO films. When the AZO films were annealed at the temperature of 300 $^{\circ}C$ for lhr in a hydrogen atmosphere, the resistivity decreased from $2.60{\times}10^{-3}\;{\Omega}cm$ to $8.42{\times}l0^{-4}\;{\Omega}cm$ for the film deposited in pure Ar gas ambient. Under the same annealing conditions of temperature and hydrogen ambient, the resistivity of AZO films deposited in the $Ar+H_2$ gas mixture decreased from $8.22{\times}l0^{-4}\;{\Omega}cm$ to $4.25{\times}l0^{-4}\;{\Omega}cm$. The lowest resistivity of $4.25{\times}l0^{-4}\;{\Omega}cm$ was obtained by adding hydrogen gas to the deposition and annealing process. X-ray diffraction (XRD) pattern of all films showed preferable growth orientation of (002) plane. The average transmittance is above 85 % and in the range of 400-1000 nm for all films.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.50-52
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• 2006

본 논문은 고성능 다결정 실리콘(Poly-Si) 박막 트랜지스터 (Thin Film Transistor)에서 단일 수직 그레인 경계(Single Perpendlcular Grain Boundary)가 고온 캐리어 스트레스(Hot Carrier Stress) 및 정전류 안정성 평가에서 어떠한 효과를 보이는가에 대해서 살펴보았다. 고온 캐리어 스트레스 하에서($V_G=V_{TH}+1V,\;V_D$ =12V),그레이 경계가 없는 다결정 실리콘 TFT와 비교했을 때 그레인 경계를 가지고 있는 다결정 실리를 TFT는 전기 전도(Electric Conduction)에 작용하는 자유 캐리어(Free Carrier)의 개수가 적기 때문에 상대적으로 더욱 우수한 전기적 특성을 나타낸다. 먼저 1000초 동안 고온 캐리어 스트레스를 가해준 결과 단일 그레인 경계를 가진 다결정 실리콘에서의 트랜스 컨덕턴스(Transconductance)의 이동 정도는 5% 미만으로 확인되었다. 반면에 같은 스트레스 조건 하에서 그레인 경계가 존재하지 않는 다결정 실리콘의 경우에는 그 이동 정도가 약 25%에 달하는 것으로 측정되었다. 다음으로 정전류 스트레스(Constant Current Stress) 인가시, 수직형 그레인 경계가 채널 영역 내에 존재하지 않는 다결정 실리콘 TFT는 드레인 접합 부분의 전계 세기를 비교했을 때, 그레인 경계를 가지고 있는 다결정 실리콘 TFT보다 상대적으로 낮은 원 인 때문에 적게 열화되는(Degraded) 특성을 확인할 수 있었다.