• Journal of Electrical Engineering and Technology
• /
• v.9 no.6
• /
• pp.2070-2078
• /
• 2014

In this work, the frequency response of gate-all-around (GAA) Ge/GaAs heterojunction tunneling field-effect transistor (TFET) with hetero-gate-dielectric (HGD) and pnpn channel doping profile has been analysed by technology computer-aided design (TCAD) device-circuit mixed-mode simulations, with comparison studies among ppn, pnpn, and HGD pnpn TFET devices. By recursive tracing of voltage transfer curves (VTCs) of a common-source (CS) amplifier based on the HGD pnpn TFET, the operation point (Q-point) was obtained at $V_{DS}=1V$, where the maximum available output swing was acquired without waveform distortion. The slope of VTC of the amplifier was 9.21 V/V (19.4 dB), which mainly resulted from the ponderable direct-current (DC) characteristics of HGD pnpn TFET. Along with the DC performances, frequency response with a small-signal voltage of 10 mV has been closely investigated in terms of voltage gain ($A_v$), unit-gain frequency ($f_{unity}$), and cut-off frequency ($f_T$). The Ge/GaAs HGD pnpn TFET demonstrated $A_v=19.4dB$, $f_{unity}=10THz$, $f_T=0.487$ THz and $f_{max}=18THz$.

• Journal of IKEEE
• /
• v.23 no.2
• /
• pp.704-709
• /
• 2019

In this paper, the electrical characteristics of tunneling field effect transistor(TFET) was studied for different annealing conditions. The TFET samples annealed using hydrogen forming gas(4 %) and Deuterium($D_2$) forming gas(4 %). All the measurements were conducted in noise shielded environment. The results show that subthreshold slope(SS) decreased by 33 mV/dec after annealing process compared to before annealing. Under various temperature range, the noise is improved by average of 31.2 % for 10 atm Deuterium gas at $V_G=3V$ condition. It is also noticed that, post metal annealing with $D_2$ gas reduces the noise by average of 30.7 % at $I_D=100nA$ condition.

• Proceeding of EDISON Challenge
• /
• 2013.04a
• /
• pp.224-227
• /
• 2013

본 연구에서는 S/D이 n+/n+로 구성된 CNT-MOSFETs, 금속으로 이루어진 SB-CNTFETs와 p+/n+로 구성된 CNT-TFETs에 대한 각각의 $I_d-V_g$ 특성과 포텐셜 프로파일을 확인하였다. 그리고 각 소자의 특성 및 특징을 연구하고, 이 중에서 BTB에 가장 큰 영향을 받는 CNT-TFETs의 특성을 $V_{DS}$, 분자 비대칭성과 $T_{ox}$에 따른 특성 변화를 연구하였다. 그 결과 예상과 다르게 오히려 작은 $V_{DS}$와 큰 $E_g$을 가질 때, 향상된 SS를 가진다는 것을 확인 할 수 있었다. 특히, (7,0) CNT-TFETs에서 비록 $I_d$는 작지만, SS를 57mV/dec까지 개선할 수 있었다. 또한, $T_{ox}$를 얇게 하면, 비록 60 mV/dec 이하의 결과는 보여주지 못했지만, SS와 Ion 모두 개선할 수 있음을 확인할 수 있었다.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.2
• /
• pp.655-661
• /
• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a surrounding gate tunnel field effect transistor (TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunneling generation rate and thus we numerically extract the tunneling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

• Journal of information and communication convergence engineering
• /
• v.19 no.4
• /
• pp.263-268
• /
• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.2
• /
• pp.271-276
• /
• 2017

The triple-gate tunnel FETs encapsulated with an epitaxial layer (EL TFETs) is proposed to lower the subthreshold swing of the TFETs. Furthermore, the band-to-band tunneling based on the maximum electric-field can occur thanks to the epitaxial layer wrapping the Si fin. The performance and mechanism of the EL TFETs are compared with the previously proposed TFET based on simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.10a
• /
• pp.170-171
• /
• 2016

A surface potential model is introduced for L-shaped tunnel field-effect-transistor(L-TFET). Excellent agreement is obtained when model results are compared with TCAD data.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.2
• /
• pp.230-238
• /
• 2017

We have proposed an InGaAs-based gate-all-around (GAA) tunneling field-effect transistor (TFET) with a stacked dual-metal gate (DMG). The electrical performances of the proposed TFET are evaluated through technology computer-aided design (TCAD) simulations. The simulation results show that the proposed TFET demonstrates improved DC performances including high on-state current ($I_{on}$) and steep subthreshold swing (S), in comparison with a single-metal gate (SMG) TFET with higher gate metal workfunction, as it has a thinner source-channel tunneling barrier width by low workfunction of source-side channel gate. The effects of the gate workfunction on $I_{on}$, the off-state current ($I_{off}$), and S in the DMG-TFETs are examined. The DMG-TFETs with PNPN structure demonstrate outstanding DC performances and RF characteristics with a higher n-type doping concentration in the $In_{0.8}Ga_{0.2}As$ source-side channel region.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.5
• /
• pp.682-687
• /
• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• Vacuum Magazine
• /
• v.3 no.3
• /
• pp.15-18
• /
• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.