JSTS:Journal of Semiconductor Technology and Science

  • 제17권2호
  • /
  • Pages.230-238
  • /
  • 2017
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지
DOI QR코드

DOI QR Code

InGaAs-based Tunneling Field-effect Transistor with Stacked Dual-metal Gate with PNPN Structure for High Performance

  • Kwon, Ra Hee (School of Electronics Engineering, Kyungpook National University) ;
  • Lee, Sang Hyuk (School of Electronics Engineering, Kyungpook National University) ;
  • Yoon, Young Jun (School of Electronics Engineering, Kyungpook National University) ;
  • Seo, Jae Hwa (School of Electronics Engineering, Kyungpook National University) ;
  • Jang, Young In (School of Electronics Engineering, Kyungpook National University) ;
  • Cho, Min Su (School of Electronics Engineering, Kyungpook National University) ;
  • Kim, Bo Gyeong (School of Electronics Engineering, Kyungpook National University) ;
  • Lee, Jung-Hee (School of Electronics Engineering, Kyungpook National University) ;
  • Kang, In Man (School of Electronics Engineering, Kyungpook National University)
  • 투고 : 2016.08.24
  • 심사 : 2016.11.01
  • 발행 : 2017.04.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

We have proposed an InGaAs-based gate-all-around (GAA) tunneling field-effect transistor (TFET) with a stacked dual-metal gate (DMG). The electrical performances of the proposed TFET are evaluated through technology computer-aided design (TCAD) simulations. The simulation results show that the proposed TFET demonstrates improved DC performances including high on-state current ($I_{on}$) and steep subthreshold swing (S), in comparison with a single-metal gate (SMG) TFET with higher gate metal workfunction, as it has a thinner source-channel tunneling barrier width by low workfunction of source-side channel gate. The effects of the gate workfunction on $I_{on}$, the off-state current ($I_{off}$), and S in the DMG-TFETs are examined. The DMG-TFETs with PNPN structure demonstrate outstanding DC performances and RF characteristics with a higher n-type doping concentration in the $In_{0.8}Ga_{0.2}As$ source-side channel region.

키워드

참고문헌

  1. A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, "Tunnel field-effect transistor without gate-drain overlap," Applied Physics Letters, Vol.91, No.5, pp.053102-1-053102-3, Jul., 2007. https://doi.org/10.1063/1.2757593
  2. Y. J. Yoon, J. H. Seo, S. Cho, H.-I. Kwon, J.-H. Lee, and I. M. Kang, "Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications," Journal of Semiconductor Technology and Science, Vol.16, No.2, pp.172-178, April. 2016. https://doi.org/10.5573/JSTS.2016.16.2.172
  3. U. E. Avci, D. H. Morris, and I. A. Young, "Tunneling Field-Effect Transistors: Prospects and Challenges," Journal of the Electron Devices Society, Vol.3, No.3, pp.88-95, May., 2015. https://doi.org/10.1109/JEDS.2015.2390591
  4. R. Iida, S.-H. Kim, M. Yokoyama, N. Taoka, S.-H. Lee, M. Takenaka, and S. Takagi, "High transconductance self-aligned gate-last surface channel $In_{0.53}Ga_{0.47}As$ MOSFET," Electron Devices Meeting, 2011. IEDM Technicla Digest. IEEE International, 5-7, pp.13.2.1-13.2.4, Dec., 2011.
  5. R. Iida, S.-H. Kim, M. Yokoyama, N. Taoka, S.-H. Lee, M. Takenaka, and S. Takagi, "Planar-type $In_{0.53}Ga_{0.47}As$ channel band-to-band tunneling metal-oxidesemiconductor field-effect transistors," Journal of Applied Physics, Vol.110, No.12, pp.124505-1-124505-8, Dec., 2011. https://doi.org/10.1063/1.3668120
  6. Y. Sun, E. W. Kiewra, S. J. Koester, N. Ruiz, A. Callegari, K. E. Fogel, D. K. Sadana, J. Fompeyrine, D. J. Webb, J.-P. Locquet, M. Sousa, R. Germann, K. T. Shiu, and S. R. Forrest, "Enhancement-Mode Buried-Channel $In_{0.7}Ga_{0.3}As/In_{0.52}Al_{0.48}As$ MOSFETs With High-${\kappa}$ Gate Dielectrics," IEEE Electron Device Letters, Vol.28, No.6, pp.473-475, June., 2007. https://doi.org/10.1109/LED.2007.896813
  7. H. Zhao, Y. Chen, Y. Wang, F. Zhou, F. Xue, and J. Lee, "InGaAs Tunneling Field-Effect-Transistors With Atomic-Layer-Deposited Gate Oxides," IEEE Transactions on Electrin Devices, Vol.58 No.9, pp.2990-2995, Sept., 2011. https://doi.org/10.1109/TED.2011.2159385
  8. A. S. Verhulst, B. Soree, D. Leonelli, W. G. Vandenberghe, and G. Groeseneken, "Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor," Journal of Applied Physics, Vol.107, No. 2, pp.024518-1-024518-8, Jan., 2010. https://doi.org/10.1063/1.3277044
  9. K. boucart and A. M. Ionescu, "Double-Gate Tunnel FET With High-${\kappa}$ Gate Dielectric," IEEE Transactions on Electron Devices, Vol.54, No.7, pp.1725-1733, July., 2007. https://doi.org/10.1109/TED.2007.899389
  10. Wataru Saito, Yoshiharu Takada, Masahiko Kuraguchi, Kunio Tsuda, and Ichiro Omura, "Short-Channel Tunneling Field-Effect Transistor with Drain-Overlap and Dual-Metal Gate Structure for Low-Power and High-Speed Operations," Journal of Nanoscience and Nanotechnology, Vol.15, No.10, pp.7430-7435, Oct., 2015. https://doi.org/10.1166/jnn.2015.11146
  11. N. Cui, R. Liang, and J. Xu, "Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation," Applied Physics Letters, Vol.98, No.14, pp.142105-1-142105-3, Apr., 2011. https://doi.org/10.1063/1.3574363
  12. N. Cui, R. Liang, and J. Xu, "Single Grain Boundary Dopingless PNPN Tunnel FET on Recrystallized Polysilicon: Proposal and Theoretical Analysis," IEEE Journal of the Electron Devices Society, Vol.3, No.3, pp.291-296, May., 2015. https://doi.org/10.1109/JEDS.2015.2392618
  13. D. B. Abdi and M. J. Kumar, "In-Built $N^+$ Pocket p-n-p-n Tunnel Field-Effect Transistor," IEEE Electron Device Letters, Vol.35, No.12, pp.1170-1172, Dec., 2014. https://doi.org/10.1109/LED.2014.2362926
  14. Y. J. Kim, Y. J. Yoon, J. H. Seo, S. M Lee, S. Cho, J.-H. Lee, and I. M. Kang, "Effect of Ga fraction in InGaAs channel on performances of gate-all-around tunneling field-effect transistor," Semiconductor Science and Technology, Vol.30, No.1, pp. 015006-1-015006-6, Nov., 2014. https://doi.org/10.1088/0268-1242/30/1/015006
  15. ATLAS User's Manual, SILVACO International, Feb., 2016.
  16. S. Cho and I. M. Kang, "Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics," Current Applied Physics, Vol.12, No.3, pp.673-677, May., 2012. https://doi.org/10.1016/j.cap.2011.10.003
  17. J. H. Seo, Y. J. Yoon, S. Lee, J.-H. Lee, S. Cho, and I. M. Kang, "Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling fieldeffect transistor (TFET)," Current Applied Physics, Vol.15, No.3, pp.208-212, May., 2015. https://doi.org/10.1016/j.cap.2014.12.013
  18. S. Cho, K. R. Kim, B.-G. Park, and I. M. Kang, "Non-Quasi-Static Modeling of Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistor and Its Model Verification up to 1 THz," Japanese Journal of Applied Physics, Vol.49, No.11, pp.110206-1-110206-3, Nov., 2010. https://doi.org/10.1143/JJAP.49.110206
  19. Y. Yang, X. Tong, L.-T. Yang, P.-F. Guo, L. Fan, and Y.-C. Yeo, "Tunneling Field-Effect Transistor: Capacitance Components and Modeling," IEEE Electron Device Letters, Vol.31, No.7, pp.752-754, Jul., 2010. https://doi.org/10.1109/LED.2010.2047240