• 지능정보연구
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• 제6권1호
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• pp.113-128
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• 2000

This paper presents a first year report of an ongoing multi-year project to develop a systolic parallel simulation system for dynamic traffic assignment. The fundamental approach to the simulation is systolic parallel processing based on autonomous agent modeling. Agents continuously act on their own initiatives and access to database to get the status of the simulation world. Various agents are defined in order to populate the simulation world. In particular existing modls and algorithm were incorporated in designing the behavior of relevant agents such as car-following model headway distribution Frank-Wolf algorithm and so on. Simulation is based on predetermined routes between centroids that are computed off-line by a conventional optimal path-finding algorithm. Iterating the cycles of optimization-then-simulation the proposed system will provide a realistic and valuable traffic assignment. Gangnum-Gu district in Seoul is selected for the target are for the modeling. It is expected that realtime traffic assignment services can be provided on the internet within 3 years.

• 한국정보처리학회논문지
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• 제6권5호
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• pp.1219-1224
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• 1999

This paper derived Montgomery's parallel algorithms for modular multiplication based on Walter's and Iwamura's method, and compared data dependence graph of each parallel algorithm. Comparing the result, Walter's parallel algorithm has small computational index in data dependence graph, so it is selected and used to computed spatial and temporal pipelining diagrams with each projection direction for designing expansible bit-level systolic array. We also evaluated internal operation of proposed expansible systolic array C++ language.

• 전자공학회논문지C
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• 제34C권10호
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• pp.36-42
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• 1997

In the whole world, the research about the VLSI implementation of motion estimation algorithm is progressed to actively full (brute force) search algorithm research with the development of systolic array possible to parallel and pipeline processing. But, because of processing time's limit in a field to handle a huge data quantily such as a high definition television, many problems are happened to full search algorithm. In the paper, as a fast processing to using parallel scheme for the serial input image data, motion estimator of systolic array structure verifying that processing time is improved in contrast to the conventional full search algorithm.

• 한국산업정보학회논문지
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• 제5권3호
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• pp.117-124
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• 2000

시스톨릭 어레이는 간단한 연산능력을 가진 처리요소들이 정규적이고 국부적인 통신 선들로 연결된 병렬처리 시스템이다. 시스톨릭 어레이는 인공신경망에서 고밀하게 연결된 뉴런으로 인하여 발생하는 뉴런간의 복잡한 통신 문제를 해결하는 가장 좋은 방법 중의 하나로 알려져 있다. 본 논문에서는 주어진 뉴런수에 적합한 역전파 인공신경망을 자동으로 생성하는 시스톨릭 어레이 시뮬레이터를 설계하고 구현한다. 시뮬레이터의 애니메이션 기법을 이용하여, 설계된 시스틀릭 어레이 상에서의 역전파 알고리즘의 실행 상황을 사용자들이 단계별로 쉽게 관찰할 수 있다. 또한, 시뮬레이터는 역전파 알고리즘의 전 방향, 역 방향 연산을 각각 따로 실행시키거나, 병렬로 실행하게 할 수 있다. 병렬 실행은 입력 자료를 연속적으로 입력받아 시스톨릭 어레이의 모든 처리요소들에서 역전파 알고리즘의 양방향 전파를 동시에 실행시킴으로써 가능하다.

• International Journal of Contents
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• 제9권1호
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 1998년도 가을 학술발표논문집 Vol.25 No.2 (3)
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• pp.691-693
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• 1998

A parallel processing systolic array reduces execution time of the Back-propagation ANN. But, systolic array must be designed whenever the number of neurons in the ANN differ. To use the systolic array which is aready designed ad a fixed size VLSI chip, partition of the problem size systolic array must be performed. This paper presents a design method of the fixed size systolic array for the Back-propagation algorthm using LSGP and LPGS partion method

• Journal of Communications and Networks
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• 제13권5호
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

• 정보학연구
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• 제10권3호
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.

• 전자공학회논문지B
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• 제30B권7호
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.