• Molecules and Cells
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• 제44권2호
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• pp.101-115
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• 2021

The INO80 chromatin remodeling complex has roles in many essential cellular processes, including DNA replication. However, the mechanisms that regulate INO80 in these processes remain largely unknown. We previously reported that the stability of Ino80, the catalytic ATPase subunit of INO80, is regulated by the ubiquitin proteasome system and that BRCA1-associated protein-1 (BAP1), a nuclear deubiquitinase with tumor suppressor activity, stabilizes Ino80 via deubiquitination and promotes replication fork progression. However, the E3 ubiquitin ligase that targets Ino80 for proteasomal degradation was unknown. Here, we identified the C-terminus of Hsp70-interacting protein (CHIP), the E3 ubiquitin ligase that functions in cooperation with Hsp70, as an Ino80-interacting protein. CHIP polyubiquitinates Ino80 in a manner dependent on Hsp70. Contrary to our expectation that CHIP degrades Ino80, CHIP instead stabilizes Ino80 by extending its half-life. The data suggest that CHIP stabilizes Ino80 by inhibiting degradative ubiquitination. We also show that CHIP works together with BAP1 to enhance the stabilization of Ino80, leading to its chromatin binding. Interestingly, both depletion and overexpression of CHIP compromise replication fork progression with little effect on fork stalling, as similarly observed for BAP1 and Ino80, indicating that an optimal cellular level of Ino80 is important for replication fork speed but not for replication stress suppression. This work therefore idenitifes CHIP as an E3 ubiquitin ligase that stabilizes Ino80 via nondegradative ubiquitination and suggests that CHIP and BAP1 act in concert to regulate Ino80 ubiquitination to fine-tune its stability for efficient DNA replication.

• 한국생산제조학회지
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• 제23권6호
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• pp.609-617
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• 2014

We have studied a chip-on-board LED lighting optical system for various luminous-intensity-distribution angles of the LED. An optical system that can accept different LEDs was made to reduce the systems's weight and size as we selected the chip-on-board LED, which is easy to apply to optical systems, unlike existing package-on-board LEDs. The luminous-intensity-distribution angles were $45^{\circ}$, $60^{\circ}$, $90^{\circ}$, and $120^{\circ}$. We researched these four types of optical systems. The $45^{\circ}$ and $60^{\circ}$ units were developed into reflectors, and the $90^{\circ}$ and $120^{\circ}$ units, into lenses. We checked the performance of the designed optical system through simulation and made a mock-up. Then we made a prototype of the chip-on-board LED high bay for use with the mock-up. After measuring its performance, we tested the luminous-intensity-distribution angles and compared them with simulation data. The resulting prototype was developed considering brightness, light uniformity, age, and economics which are suitable for a factory environment.

• 한국정보과학회논문지:시스템및이론
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• 제32권11_12호
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• pp.629-638
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• 2005

시스템 온 칩 설계에서 온 칩 버스는 전체 시스템의 성능을 결정하는 중요한 요소이다. 특히 프로세서, DSP 및 멀티미디어 IP와 같이 보다 높은 버스 대역폭을 요구하는 IP가 사용될 경우 온 칩 버스의 대역폭 문제는 더욱 심각해진다. 이에 따라 최근 ARM 사에서는 고성능 온 칩 버스 구조인 ML-AHB 버스 매트릭스를 제안하였다. ML-AHB 버스 매트릭스는 시스템 내의 다중 마스터와 다중 슬레이브간의 병렬적인 접근 경로를 제공하여 전체 버스 대역폭을 증가시켜주고, 최근 많은 프로세서 요소들을 사용하는 휴대형 기기 및 통신 기기 등에 적합한 고성능 온 칩 버스 구조이다. 하지만 내부 컴포넌트인 입력 스테이지와 무어 타입으로 구현된 중재 방식으로 인해 마스터가 새로운 전송을 수행할 때 또는 슬레이브 레이어를 변경할 때 마다 항상 1 클럭 사이클 지연 현상이 발생된다. 본 논문에서는 이러한 문제점을 해결하기 위해 기존 ML-AHB 버스 매트릭스 구조를 개선하였다. 기존 버스 매트릭스 구조에서 입력 스테이지를 제거하고, 개선된 구조에 적합하도록 중재 방식을 변경하여 1 클럭 사이클 지연 문제를 해결하였다. 개선된 결과 4-beat incrementing 버스트 타입으로 다수의 트랜잭션을 수행할 경우, 기존 ML-AHB 버스 매트릭스에 비해 전체 버스 트랜잭션 종료 시간 및 평균 지연 시간이 각각 약 $20\%,\;24\%$ 정도 짧아졌다. 또한 FPGA의 슬라이스 수는 기존의 ML-AHB 버스 매트릭스보다 약 $22\%$ 정도 감소하였고, 클럭 주기도 약 $29\%$ 정도 짧아졌다.

• 제어로봇시스템학회논문지
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• 제6권10호
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• pp.903-910
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• 2000

In this paper, we describe a slave chip based on the Profibus-DP protocol and a system board to verify the developed slave chip. The Profibus-DP protocol is designed using VHDL and implemented on FPGA. The system board adopting the developed FPGA is designed FPGA is designed in which the firmware is implemented on Intel 8051 by using C language. Among the Profibus-DP protocols, low level layers from the physical layer to the data link layer is implemented in the form of hardware that we are able to greatly reduce the CPU load in processing protocols, and then higher layers could be processed by software. These technologies result in an IP to make terminal devices in the distributed control systems. Therefore, many digital logics as well as communication logics can be implemented onto SOC(System On a Chip) and it could be applied to various fieldbus-related areas.

• 제어로봇시스템학회논문지
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• 제10권3호
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• pp.261-266
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• 2004

Recently, a variety of intelligent robots are developed for the personal purpose beyond the industrial application. These intelligent robots have ranges of sensors, actuators, and control algorithms to their application. In this paper we propose a reconfigurable robot controller, $SR^2$c (The SOPC-based Reconfigurable Robot Controller), based on SOPC (System on a Programmable Chip), that can be reconfigurable easily by software. The proposed robot controller contains not only a processing module but also robot-specific IP's. To show a feasibility of the proposed robot controller, a small entertainment robot, Wizard-4 is implemented with a single chip controller as proposed in this paper.

• International Journal of Control, Automation, and Systems
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• 제4권5호
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• pp.567-574
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• 2006

This paper presents the hardware implementation of a neural network controller for a nonlinear system with a micro-controller unit (MCU) and a field programmable gate array (FPGA) chip. As an on-line learning algorithm of a neural network, the reference compensation technique has been implemented on an MCU, while PID controllers with other functions such as counters and PWM generators are implemented on an FPGA chip. Interface between an MCU and a field programmable gate array (FPGA) chip has been developed to complete hardware implementation of a neural controller. The developed neural control hardware has been tested for balancing the inverted pendulum while controlling a desired trajectory of a cart as a nonlinear system.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.28-36
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• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• Current Optics and Photonics
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• 제5권2호
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• pp.147-154
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• 2021

Microfluidic chip technology is a research focus in biology, chemistry, and medicine, for example. However, microfluidic chips are rarely applied in imaging, especially in ghost imaging. Thus in this work we propose a ghost-imaging system, in which we deploy a novel microfluidic chip modulator (MCM) constructed of double-layer zigzag micro pipelines. While in traditional situations a spatial light modulator (SLM) and supporting computers are required, we can get rid of active modulation devices and computers with this proposed scheme. The corresponding simulation analysis verifies good feasibility of the scheme, which can ensure the quality of data transmission and achieve convenient, fast ghost imaging passively.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 추계학술대회 논문집
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• pp.276-280
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• 2001

In the development of Chip Mounter(C/M), much interests have risen regarding how to decrease the operation time of mounting the different chips on the printed circuit board(PCB). The existing method to determine the time sequence of teaching C/M was to follow the procedure which was made by the operater. IN this study, a new but effective algorithm has been developed and employed in SCM-130 Chip Mounter and its online programming had reduced the mounting time significantly and provided the basis for the future online CAD/CAM system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.