References
- B. Muller, J. Reinhardt, and M. Strickland, Neural Networks: An Introduction (Physics of Neural Networks). Springer, 2002.
- A. K. Jain, R. P. W. Duin, and J. C. Mao, “Statistical pattern recognition: A review,” IEEE Trans. Pattern Analysis and Machine Intelligence, Vol.22, No.1, pp.4-37, Jan. 2000. https://doi.org/10.1109/34.824819
- D. Graupe, principles of artificial neural networks, World Scientific, 2007.
- I. A. Basheer and M. Hajmeer, “Artificial neural networks: Fundamentals, computing, design, and application,” Journal of Microbiological Methods, Vol.43, pp.3-31, 2000. https://doi.org/10.1016/S0167-7012(00)00201-3
- C. S. Lindsey, “Neural networks in hardware: Architectures, products and applications,” in lecture notes of Neural Networks, Aug. 2002.
- Q. Wang, A. Li, Z. C. Li, and Y. Wan, “A design and implementation of reconfigurable architecture for neural networks based on systolic arrays,” Advances in Neural Networks, No.3973, pp. 1328-1333, 2006.
- L. Smith, “Implementing Neural Models in Silicon,” Handbook of Nature-Inspired and Innovative Computing Section 11, Springer, 2006.
- S. Vitabile, A. Gentile, G. B. Dammone, and F. Sorbello, “MlP neural network implementation on a simd architecture,” Neural Nets, Vol.2486, 2002.
- W. J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” in Proc. of the 38th Design Automation Conference (DAC), Jun. 2001.
- L. Benini and G. D. Micheli, Networks On Chips: Technology and tools, Morgan Kaufmann, 2005.
- C. Ciordas, K. Goossens, T. Basten, A. Radulescu, and A. Boon, “Transaction monitoring in networks on chip: The on-chip run-time perspective,” Proc. IES'06, pp.1-10, Oct. 2006.
- J. Nurmi, H. Tenhunen, J. Isoaho, and A. Jantsch, Interconnect-Centric Design for Advanced SOC and NOC. Kluwer Academic Publisher, 2004.
- Y. P. Dong, C. Li, K. Kumai, Y. H. Li, Y. Wang, and T. Watanabe, “A New Flexible Network on Chip Architecture for Mapping Complex Feedforward Neural Network,” Journal of Signal Processing, Vol.13, No.5, 2009. (to appear)
- Y. P. Dong, Y. H. Li, Y. Wang, and T. Watanabe, “Low Power and High Speed Network on Chip Architecture for BP Neural Network,” Proc. ITCCSCC' 09, pp. 298-301, Jul. 2009.
- A. Jantsch and H. Tenhunen, Networks on Chip, Kluwer Academic Publishers, 2003.
- Y. P. Dong and T. Watanabe, “Network on chip architecture for bp neural network,” Proc. IEEE ICCCAS'08, pp.1083-1087, May 2008.
- A. Omondi and J. Rajapakse, FPGA Implementations of Neural Networks, Springer, 2006.
- H. M. Yao, H. B. Vuthaluru, M. O. Tade, and D. Djukanovic, “Artificial neural network-based prediction of hydrogen content of coal in power station boilers,” Fuel, Vol.84, No.12-13, pp.1535-1542, Sep. 2005.
- AlteraInc., Stratix Device Handbook, Jan. 2006.
- X. M. Chen and D. Z. Chen, “Measuring average particle size for fluidized bed reactors by employing acoustic emission signals and neural networks,” Chemical engineering and technology, Vol.31, No.1, pp.95-102, Dec. 2007.
- L. Jain, “NIRGAM,” University of Southampton UK, http://www.nirgam.ecs.soton.ac.uk.
- C.S. Lindsey and T. Lindblad, “Review of hardware neural networks: a user's perspective,” Plenary talk given at 3rd Workshop on Neural Networks, 1994.
- B. Muller, J. Reinhardt, and M. Strickland, Neural Networks: An Introduction (Physics of Neural Networks). Springer, 2002.
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