• Korean Journal of Materials Research
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• v.20 no.11
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• pp.586-591
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• 2010

Solar cells have been more intensely studied as part of the effort to find alternatives to fossil fuels as power sources. The progression of the first two generations of solar cells has seen a sacrifice of higher efficiency for more economic use of materials. The use of a single junction makes both these types of cells lose power in two major ways: by the non-absorption of incident light of energy below the band gap; and by the dissipation by heat loss of light energy in excess of the band gap. Therefore, multi junction solar cells have been proposed as a solution to this problem. However, the $1^{st}$ and $2^{nd}$ generation solar cells have efficiency limits because a photon makes just one electron-hole pair. Fabrication of all-silicon tandem cells using an Si quantum dot superlattice structure (QD SLS) is one possible suggestion. In this study, an $SiO_x$ matrix system was investigated and analyzed for potential use as an all-silicon multi-junction solar cell. Si quantum dots with a super lattice structure (Si QD SLS) were prepared by alternating deposition of Si rich oxide (SRO; $SiO_x$ (x = 0.8, 1.12)) and $SiO_2$ layers using RF magnetron co-sputtering and subsequent annealing at temperatures between 800 and $1,100^{\circ}C$ under nitrogen ambient. Annealing temperatures and times affected the formation of Si QDs in the SRO film. Fourier transform infrared spectroscopy (FTIR) spectra and x-ray photoelectron spectroscopy (XPS) revealed that nanocrystalline Si QDs started to precipitate after annealing at $1,100^{\circ}C$ for one hour. Transmission electron microscopy (TEM) images clearly showed SRO/$SiO_2$ SLS and Si QDs formation in each 4, 6, and 8 nm SRO layer after annealing at $1,100^{\circ}C$ for two hours. The systematic investigation of precipitation behavior of Si QDs in $SiO_2$ matrices is presented.

• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.125-130
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• 2009

This paper reviews the characteristics technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.3
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• pp.332-336
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• 2024

High-energy bandgap material silicon carbide (SiC) is gaining attention as a next-generation power semiconductor material, and in particular, SiC-based MOSFETs are developed as representative power semiconductors to increase the breakdown voltage (BV) of conventional planar structures. However, as the size of SJ (Super Junction) MOSFET devices decreases and the depth of pillars increases, it becomes challenging to uniformly form the doping concentration of pillars. Therefore, a structure with different doping concentrations segmented within the pillar is being researched. Using Silvaco TCAD simulation, a SJ VVD (vertical variation doping profile) MOSFET with three different doping concentrations in the pillar was studied. Simulations were conducted for the width of the pillar and the doping concentration of N-epi, revealing that as the width of the pillar increases, the depletion region widens, leading to an increase in on-specific resistance (R_on,sp) and breakdown voltage (BV). Additionally, as the doping concentration of N-epi increases, the number of carriers increases, and the depletion region narrows, resulting in a decrease in R_on,sp and BV. The optimized SJ VVD MOSFET exhibits a very high figure of merit (BFOM) of 13,400 KW/cm², indicating excellent performance characteristics and suggesting its potential as a next-generation highperformance power device suitable for practical applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.6
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• pp.345-348
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• 2017

In this work, static characteristics of 4H-SiC SJ-ACCUFETs were obtained by adjusting the p-pillar region. The structure of this SJ-ACCUFET was designed by using a two-dimensional simulator. The static characteristics of SJ-ACCUFET, such as the breakdown voltages, on-resistance, and figure of merits, were obtained by varying the p-pillar doping concentration from $1{\times}10^{15}cm^{-3}$ to $5{\times}10^{16}cm^{-3}$ and the thickness from $0{\mu}m$ to $9{\mu}m$. The doping concentration and the thickness of p-pillar region are closely related to the break down voltage and on-resistance and threshold voltages. Hence a silicon carbide SJ-ACCUFET structure with highly intensified breakdown voltages and low on-resistances with good figure of merits can be achieved by optimizing the p-pillar thickness and doping concentration.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.6
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• pp.558-565
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• 2015

Gallium nitride high-electron mobility transistor (GaN HEMT) is the strongest candidate for replacing Si MOSFET. Comparing the figure of merit (FOM) of GaN with the state-of-the-art super junction Si MOSFET, the FOM is much better because of the wide band gap characteristics and the heterojunction structure. Although GaN HEMT has many benefits for the power conversion system, the performance of the power conversion system with the GaN HEMT is sensitive because of its low threshold voltage ($V_{th}$) and even lower parasitic capacitance. This study examines the characteristics of a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT. The problem of unoptimized dead time is analyzed on the basis of the output capacitance of GaN HEMT. In addition, the printed circuit board (PCB) layout consideration is analyzed to reduce the negative effects of parasitic inductance. A comparison of the experimental results is provided to validate the dead time and PCB layout analysis for a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT.

• Korean Journal of Materials Research
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• v.20 no.11
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• pp.606-610
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• 2010

Films consisting of a silicon quantum dot superlattice were fabricated by alternating deposition of silicon rich silicon nitride and $Si_3N_4$ layers using an rf magnetron co-sputtering system. In order to use the silicon quantum dot super lattice structure for third generation multi junction solar cell applications, it is important to control the dot size. Moreover, silicon quantum dots have to be in a regularly spaced array in the dielectric matrix material for in order to allow for effective carrier transport. In this study, therefore, we fabricated silicon quantum dot superlattice films under various conditions and investigated crystallization behavior of the silicon quantum dot super lattice structure. Fourier transform infrared spectroscopy (FTIR) spectra showed an increased intensity of the $840\;cm^{-1}$ peak with increasing annealing temperature due to the increase in the number of Si-N bonds. A more conspicuous characteristic of this process is the increased intensity of the $1100\;cm^{-1}$ peak. This peak was attributed to annealing induced reordering in the films that led to increased Si-$N_4$ bonding. X-ray photoelectron spectroscopy (XPS) analysis showed that peak position was shifted to higher bonding energy as silicon 2p bonding energy changed. This transition is related to the formation of silicon quantum dots. Transmission electron microscopy (TEM) and electron spin resonance (ESR) analysis also confirmed the formation of silicon quantum dots. This study revealed that post annealing at $1100^{\circ}C$ for at least one hour is necessary to precipitate the silicon quantum dots in the $SiN_x$ matrix.