• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.26-31
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• 2023

We investigated the impact of NF₃ / H₂O remote plasma dry cleaning conditions on the SiO₂ etching rate at different preparation states during the fabrication of ultra-large-scale integration (ULSI) devices. This included consideration of factors like Si crystal orientation prior to oxidation and three-dimensional structures. The dry cleaning process were carried out varying the parameters of pressure, NF₃ flow rate, and H₂O flow rate. We found that the pressure had an effective role in controlling anisotropic etching when a thin SiO₂ layer was situated between Si₃N₄ and Si layers in a multilayer trench structure. Based on these observations, we would like to provide further guidelines for implementing the dry cleaning process in the fabrication of semiconductor devices having 3D structures.

• Korean Journal of Materials Research
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• v.26 no.9
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• pp.455-459
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• 2016

The deposition process for the gap-filling of sub-micrometer trenches using DMDMOS, $(CH_3)_2Si(OCH_3)_2$, and $C_xH_yO_z$ by flowable chemical vapor deposition (F-CVD) is presented. We obtained low-k films that possess superior gap-filling properties on trench patterns without voids or delamination. The newly developed technique for the gap-filling of submicrometer features will have a great impact on IMD and STI for the next generation of microelectronic devices. Moreover, this bottom up gap-fill mode is expected to be universal in other chemical vapor deposition systems.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.441-446
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• 2003

The chemical mechanical polishing (CMP) process is now widely employed in the ultra large scale integrated (ULSI) semiconductor fabrication. Especially, shallow trench isolation (STI) has become a key isolation scheme for sub-0.13/0.10${\mu}{\textrm}{m}$ CMOS technology. The most important issues of STI-CMP is to decrease the various defects such as nitride residue, dishing, and tom oxide. To solve these problems, in this paper, we studied the planarization characteristics using slurry additive with the high selectivity between $SiO_2$ and $Si_3$$N_4$ films for the purpose of process simplification and in-situ end point detection. As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also, we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of STI-CMP process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.305-310
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• 2008

Deep trench etching of silicon was investigated as a function of RF source power, DC bias voltage, $C_4F_8$ gas flow rate, and $O_2$ gas addition. On increasing the RF source power from 300 W to 700 W, the etch rate was increased from $3.52{\mu}m/min$ to $7.07{\mu}m/min$. The addition of $O_2$ gas improved the etch rate and the selectivity. The highest etch rate is achieved at the $O_2$ gas addition of 12 %, The selectivity to PR was 65.75 with $O_2$ gas addition of 24 %. At DC bias voltage of -40 V and $C_4F_8$ gas flow rate of 30 seem, We were able to achieve etch rate as high as $5.25{\mu}m/min$ with good etch profile.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.68-68
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• 2011

As feature size is smaller, new technology are needed in semiconductor factory such as gap-fill technology for sub 100nm, development of ALD equipment for Cu barrier/seed, oxide trench etcher technology for 25 nm and beyond, development of high throughput Cu CMP equipment for 30nm and development of poly etcher for 25 nm and so on. We are focus on gap-fill technology for sub-30nm. There are many problems, which are leaning, over-hang, void, micro-pore, delaminate, thickness limitation, squeeze-in, squeeze-out and thinning phenomenon in sub-30 nm gap fill. New gap-fill processes, which are viscous oxide-SOD (spin on dielectric), O3-TEOS, NF3 Based HDP and Flowable oxide have been attempting to overcome these problems. Some groups investigated SOD process. Because gap-fill performance of SOD is best and process parameter is simple. Nevertheless these advantages, SOD processes have some problems. First, material cost is high. Second, density of SOD is too low. Therefore annealing and curing process certainly necessary to get hard density film. On the other hand, film density by Flowable oxide process is higher than film density by SOD process. Therefore, we are focus on Flowable oxide. In this work, dielectric film were deposited by PECVD with TSA(Trisilylamine - N(SiH3)3) and NH3. To get flow-ability, the effect of plasma treatment was investigated as function of O2 plasma power. QMS (quadruple mass spectrometry) and FTIR was used to analysis mechanism. Gap-filling performance and flow ability was confirmed by various patterns.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.481-484
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• 1998

In this study, oxide(TEOS) CMPs were carried out for various head pressures. Table and head speeds are fixed at 25 RPM. Head pressures are 5, 7.5, 10, 12.5 PSI, and under these conditions, 1,587, 1,631, 2,556, 2,871.agns./min of oxide (TEOS) removal rates and 14.7, 18.5, 9.52, 7.9% of uniformities are obtained, respectively. Also, these experiments for local and global planarizations were done using the patterned 4" wafers. These conditions are applicable to STI(shallow trench isolation) structures and planarizations for sub-half micron lithography.aphy.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.53-53
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• 2011

As the dimension of Cu interconnects has continued to reduce, its resistivity is expected to increase at the nanoscale due to increased surface and grain boundary scattering of electrons. To suppress increase of the resistivity in nanoscale interconnects, alloying Cu with other metal elements such as Al, Mn, and Ag is being considered to increase the mean free path of the drifting electrons. The formation of Al alloy with a slight amount of Cu broadly studied in the past. The study of Cu alloy including a very small Al fraction, by contrast, recently began. The formation of Cu-Al alloy is limited in wet chemical bath and was mainly conducted for fundamental studies by sputtering or evaporation system. However, these deposition methods have a limitation in production environment due to poor step coverage in nanoscale Cu metallization. In this work, gap-filling of Cu-Al alloy was conducted by cyclic MOCVD (metal organic chemical vapor deposition), followed by thermal annealing for alloying, which prevented an unwanted chemical reaction between Cu and Al precursors. To achieve filling the Cu-Al alloy into sub-100nm trench without overhang and void formation, furthermore, hydrogen plasma pretreatment of the trench pattern with Ru barrier layer was conducted in order to suppress of Cu nucleation and growth near the entrance area of the nano-scale trench by minimizing adsorption of metal precursors. As a result, superconformal gap-fill of Cu-Al alloy could be achieved successfully in the high aspect ration nanoscale trenches. Examined morphology, microstructure, chemical composition, and electrical properties of superfilled Cu-Al alloy will be discussed in detail.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.45-51
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• 2004

We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.

• The Journal of the Petrological Society of Korea
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• v.18 no.1
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• pp.19-30
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• 2009

The main fault of Yangsan Fault Zone (YFZ) and Quaternary fault were found in a trench section with NW-SE direction at an entrance of the Sinheung village in the northern Eonyang, Ulsan, Korea. We interpreted the movement history of the southern part of the YFZ from the geometric and kinematic characteristics of basement rock's fault of the YFZ (Sinheung Fault) and Quaternary fault (Quaternary Sinheung Fault) investigated at the trench section. The trench outcrop consists mainly of Cretaceous sedimentary rocks of Hayang Group and volcanic rocks of Yucheon Group which lie in fault contact and Quaternary deposits which unconformably overlie these basement rocks. This study suggests that the movement history of the southern part of the YFZ can be explained at least by two different strike-slip movements, named as D1 and D2 events, and then two different dip-slip movements, named as D3 and D4 events. (1) D1 event: a sinistral strike-slip movement which caused the bedding of sedimentary rocks to be high-angled toward the main fault of the YFZ. (2) D2 event: a dextral strike-slip movement slipped along the high-angled beddings as fault surfaces. The main characteristic structural elements are predominant sub-horizontal slickenlines and sub-vertical fault foliations which show a NNE trend. The event formed the main fault rocks of the YFZ. (3) D3 event: a conjugate reverse-slip movement slipped along fault surfaces which trend (E)NE and moderately dip (S)SE or (N)NW. The slickenlines, which plunge in the dip direction of fault surfaces, overprint the previous sub-horizontal slickenlines. The fault is characterized by S-C fabrics superimposed on the D2 fault gouges, fault surfaces showing ramp and flat geometry, asymmetric and drag folds and collapse structures accompanied with it. The event dispersed the orientation of the main fault surface of the YFZ. (4) D4 event: a Quaternary reverse-slip movement showing a displacement of several centimeters with S-C fabrics on the Quternary deposits. The D4 fault surfaces are developed along the extensions of the D3 fault surfaces of basement rocks, like the other Quaternary faults within the YFZ. This indicates that these faults were formed under the same compression of (N)NW-(S)SE direction.