• ETRI Journal
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• v.38 no.6
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• pp.1163-1171
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• 2016

Integration technologies involving flexible substrates are receiving significant attention owing the appearance of new products regarding wearable and Internet of Things technologies. There has been a continuous demand from the industry for a reliable bonding method applicable to a low-temperature process and flexible substrates. Up to now, however, an anisotropic conductive film (ACF) has been predominantly used in applications involving flexible substrates; we therefore suggest low-temperature lead-free soldering and bonding processes as a possible alternative for flex-on-flex applications. Test vehicles were designed on polyimide flexible substrates (FPCBs) to measure the contact resistances. Solder bumping was carried out using a solder-on-pad process with Solder Bump Maker based on Sn58Bi for low-temperature applications. In addition, thermocompression bonding of FPCBs was successfully demonstrated within the temperature of $150^{\circ}C$ using a newly developed fluxing underfill material with fluxing and curing capabilities at low temperature. The same FPCBs were bonded using commercially available ACFs in order to compare the joint properties with those of a joint formed using solder and an underfill. Both of the interconnections formed with Sn58Bi and ACF were examined through a contact resistance measurement, an $85^{\circ}C$ and 85% reliability test, and an SEM cross-sectional analysis.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.235-237
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• 2007

In this paper, fabrication of Sn-3.0Ag-0.5Cu solder bumping having accurate composition and behavior of intermetallic compounds(IMCs) growth at interface between Sn-Ag-Cu bumps and Cu substrate were studied. The ternary alloy of the Sn-3.0Ag-0.5Cu solder was made by two binary(Sn-Cu, Sn-Ag) electroplating on Cu pad. For the manufacturing of the micro-bumps, photo-lithography and reflow process were carried out. After reflow process, the micro-bumps were aged at $150^{\circ}C$ during 1 hr to 500 hrs to observe behavior of IMCs growth at interface. As a different of Cu contents(0.5 or 2wt%) at Sn-Cu layer, behavior of IMCs was estimated. The interface were observed by FE-SEM and TEM for estimating of their each IMCs volume ratio and crystallographic-structure, respectively. From the results, it was found that the thickness of $Cu_3Sn$ layer formed at Sn-2.0Cu was thinner than the thickness of that layer be formed Sn-0.5Cu. After aging treatment $Cu_3Sn$ was formed at Sn-0.5Cu layer far thinner.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.49-54
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• 2001

This paper presents several UBM (Under Bump Metallurgy) systems which are currently used for wafer level solder bumping technology. The advantages and disadvantages of each UBM are summarized from the point of view of process compatability and interface morphological stability.

• Journal of Welding and Joining
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• v.18 no.4
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• pp.55-63
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• 2000

This paper presents a study of the solder bumping process. The theoretical model, based on the variational principle instead of solving the Navier-Stokes equation with moving boundaries, was developed to considered the energy dissipation in semi-solid phase and the approximate solidification time of the molten metal droplet. The simulation results revealed that the developed model could reasonably describe the collision behavior of molten metal with solid surface. Simulations were made with variation of initial droplet temperature, substrate metal and initial substrate temerature.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.21-28
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• 2004

We have demonstrated the applicability of dry film photoresist (DFR) in photolithography process for fine pitch solder bumping on the polytetrafluoroethylene (PTFE/Teflon ) printed circuit board (PCB). The copper lines were formed with 100$\mu\textrm{m}$ width and 18$\mu\textrm{m}$ thickness on the PTFE test board, and varying the gaps between two copper lines in a range of 100-200$\mu\textrm{m}$. The DFRs of 15$\mu\textrm{m}$ thickness were laminated by hot roll laminator, by varying laminating temperature from $100{\circ}C$ to 15$0^{\circ}C$ and laminating speed from 0.28-0.98cm/s. We have found the optimum process of DFR lamination on PTFE PCB and accomplished the formation of indium solder bumps. The optimum lamination condition was temperature of $150^{\circ}C$ and speed of about 0.63cm/s. And the smallest size of indium solder bump was diameter of 50$\mu\textrm{m}$ with pitch of 100$\mu\textrm{m}$.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.82-82
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• 2010

표면실장 공법을 통해 CSP 패키지를 보드에 실장 하는데 있어 무연솔더 접합부의 신뢰성에 영향을 미치는 인자 중 가장 중요한 것은 접합부에 형성되는 IMC (Intermetallic compound, 금속간화합물)인 것으로 알려져 있다. 접합부의 칩 부분에는 솔더와 칩의 UBM (Under bump metalization)이 접합하여 IMC가 형성되나, 보드 부분에는 솔더와 보드의 UBM 뿐만 아니라 그 사이에 솔더 페이스트가 함께 접합되어 IMC가 형성된다. 본 연구에서는 패키지의 신뢰성 연구를 위해 솔더 페이스트의 유무 및 두께에 따른 무연 솔더 접합부의 미세조직의 변화를 분석하였다. 본 실험에서는 Sn-3.0(Wt.%)Ag-0.5Cu 조성과 본 연구진에 의해 개발된 Sn-Ag-Cu-In 조성의 직경 $450{\mu}m$ 솔더 볼을 사용하였으며, 솔더 페이스트는 상용 Sn-3.0Ag-0.5Cu (ALPHA OM-325)를 사용하였다. 칩은 ENIG (Electroless nickel immersion gold) finish pad가 형성된 CSP (Chip scale package)를, 보드는 OSP (Organic solderability preservative)/Cu finish pad가 형성된 것을 사용하였다. 실험 방법은 보드를 솔더 페이스트 없이 플라즈마 처리 한 것, 솔더 페이스트를 $30{\mu}m$ 두께로 인쇄한 것, $120{\mu}m$의 두께로 인쇄한 것, 이렇게 3가지 조건으로 준비한 후, 솔더 볼이 bumping된 칩을 mounting하여, $242^{\circ}C$의 peak 온도 조건의 oven(1809UL, Heller)에서 reflow를 실시하여 패키지를 형성하였다. 이후 시편은 정밀 연마한 후, OM(Optical Microscopic)과 SEM(scanning electron microscope) 및 EDS(energy dispersive spectroscope)를 사용하여 솔더 접합부 IMC의 미세조직을 관찰, 분석하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.43-49
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• 2007

Thickness of intermetallic compounds and consumption rates of under bump metallurgies (UBMs) were investigated in wafer-level solder bumping with variations of UBM materials and reflow times. In the case of Cu UBM, $0.6\;{\mu}m-thick$ intermetallic compound layer was formed before reflow of Sn solder, and the average thickness of the intermetallic compound layer increased to $4\;{\mu}m$ by reflowing at $250^{\circ}C$ for 450 sec. On the contrary, the intermetallic layer had a thickness of $0.2\;{\mu}m$ on Ni UBM before reflow and it grew to $1.7\;{\mu}m$ thickness with reflowing for 450 sec. While the consumption rates of Cu UBM were 100nm/sec fur 15-sec reflow and 4.50-sec for 450-sec reflow, those of Ni UBM decreased to 28.7 nm/sec for 15-sec reflow and 1.82 nm/sec for 450-sec reflow.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.1-7
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• 2008

We studied a growth behavior of Intermetallic compounds(IMCs) during solder bumping with two reflow methods. Ti(50 nm), Cu($1{\mu}m$), Au(50 nm) and Ti(50 nm) thin films were deposited on $SiO_2$/Si wafer using the DC magnetron sputtering system as the under bump metallization(UBM). And the $5{\mu}m$ thick Cu bumps and $20{\mu}m$ thick Sn bumps were fabricated on UBM by electroplating. Sn bumps were reflowed in RTA(Rapid Thermal Annealing) system and convection reflow oven. When RTA system was used, reflow was possible without using flux and IMC thickness formed in the solder interface was thinner than that of a convectional method.