• Title/Summary/Keyword: So Chong

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A Study on Making Space of Primary School Classroom for Using Dormitory - Focused on the Abolished School - (초등학교(初等學校) 교실(敎室)의 기숙사(寄宿舍) 활용(活用)을 위한 공간구성(空間構成)에 관한 연구(硏究) - 폐교(廢校)를 중심(中心)으로 -)

  • Chong, Geon-Chai;Jang, Taek-Ju
    • Journal of the Korean Institute of Rural Architecture
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    • v.1 no.2
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    • pp.63-73
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    • 1999
  • The study is focused on making space of the abolished primary school for college dormitory in rural area which has regional type nearby city. We, firstly, analysed regional conditions and then surveyed various data for space conditions of dormitory. By surveying exterior space and interior renovation, and analysing the actual conditions of dormitory, we propose design factors and model of using facilities of the abolished primary school. So, the purpose of it is to suggest making space and a model of dormitory utilization of abolished school in regional type nearby city. It is a spacial case of re-using facilities of abolished school in rural area, but we expect that abolished school make an offer another type of using facilities.

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Model-based sliding mode tracking control of 6-6 Stewart platform manipulator

  • Lee, Chong-Won;Kim, Nag-In
    • 제어로봇시스템학회:학술대회논문집
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    • 1997.10a
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    • pp.772-775
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    • 1997
  • A high speed tracking control for 6-6 Stewart platform manipulator is performed by employing the joint-axis sliding mode control based on dynamics. Because of the complex dynamics and kinematics of Stewart platform manipulator, two computer systems, consisting of a PC and a DSP, are adopted, so that real time tasks are run in synchronous and asynchronous modes. It is experimentally proven that the proposed control system leads to an easy to implement and effective control task, and it can achieve the high performance tracking control under the high speed and severe payload condition.

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Characteristics of the ZMP for the biped robot

  • Park, Chan-Soo;Choi, Chong-Ho
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.220-224
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    • 2003
  • This is a preliminary study is to make the robot walk more stably by observing the ZMP (Zero Moment Point) of the robot when the robot stands on one leg(single support) and then on two legs(double support) and so on. The robot consists of nine DOF (Degree of freedom) with lower part of the body. It is equipped with motor drivers and force sensors inside the robot. The motors are controlled by the external PC (Intel pentium 4). By the experimental results, it is found that the robot is unstable in the instant of changing from single support to double support or from double support to single support. We use the trajectory compensation of the angle and the length of both legs to realize more stable walking.

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A Study on the Design of FFT Architecture for Ultra-Wide Band OFDM Communication System (UWB OFDM 통신 시스템 용 FFT(Fast Fourier Transform) 설계에 관한 연구)

  • Park Kye-Wan;Yoon Sang-hun;Chong Jong-Wha
    • Proceedings of the IEEK Conference
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    • 2004.06a
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    • pp.309-312
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    • 2004
  • This paper proposes the architecture of UWB OFDM communication system. More high data rate is requested in the 128-point FFT/IFFT of the UWB OFDM communication system than the conventional communication systems. So, the proposed architecture uses pipeline and parallel architecture. For a highly efficient architecture, the optimal clipping power and the input quantization bits are found in simulation. The hardware complexity of the proposed architecture is presented is consideration of Adder, Register and Complex Multiplier.

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An Efficient Semaphore Implementation Scheme for an Event

  • Sihn, Bong-sik;Han, Ki-Hee;Chong, Jong-Wha
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.443-445
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    • 2002
  • In this paper, we present a novel efficient semaphore implementation scheme which diminishes completion time of high priority tasks and improves reliability of a system. The real-time system is constrained to complete their tasks in time. Especially, the task of a hard real-time system must meet its deadline under unfavorable conditions. In this paper, the number and sort of the locked semaphores, when an event occurred, decide whether the context switch should occur or not, so higher priority tasks diminish in their completion time. The experimental results show that the proposed method gives performance improvements in finish time of high priority tasks of about 11% over the Zuberi.

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Thermal Aware Buffer Insertion in the Early Stage of Physical Designs

  • Kim, Jaehwan;Ahn, Byung-Gyu;Kim, Minbeom;Chong, Jongwha
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.4
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    • pp.397-404
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    • 2012
  • Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

Voltage Island Partitioning Based Floorplanning Algorithm

  • Kim, Jae-Hwan;Chong, Jong-Wha
    • Journal of IKEEE
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    • v.16 no.3
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    • pp.197-202
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    • 2012
  • As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.

A brief review on the recent progress of superconducting nanowire single photon detectors

  • Chong, Yonuk
    • Progress in Superconductivity and Cryogenics
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    • v.19 no.4
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    • pp.22-25
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    • 2017
  • Superconducting nanowire single photon detectors (SNSPD) have become the most competent photon-counting devices in wide range of wavelengths. Especially in the communication wavelength (infrared), SNSPD has shown unbeatable superior performance compared to the state-of-art semiconductor single photon detectors. The technology has matured enough for the last decade so that several commercial systems are now almost ready for routine use in general optics experiments. Here we summarize briefly the recent progress in this research field, and hope to motivate further research on the improvement of the device and the system. We cover the basic key concepts, device and system performances, remaining issues and possible further research directions of SNSPD.

A Kinematics Approach to 3D Graphical Interface (3D 그래픽스 인터페이스에 대한 운동학적 접근)

  • Lee, Joo-Haeng;Jang, Tae-Ik;Kim, Myung-Soo;Kim, Mansoo;Chong, Kyung Taek;Lee, Ee Taek
    • Journal of the Korea Computer Graphics Society
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    • v.2 no.2
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    • pp.53-60
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    • 1996
  • In 3D graphics interface, 3D objects and virtual camera have many degrees of freedom. We interpret the control of 3D objects and virtual camera as a problem of kinematics and inverse kinematics. It is well known that extra degrees of freedom introduce various singularities in inverse kinematics. In this paper, we approach 3D graphics interface problems by reducing redundant degrees of freedom so that the control degrees of freedom matches with the degrees of freedom in the motions of 3D objects and virtual camera.

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A Study of the Current Reference Signal Generation Circuit for Single-Phase Harmonic Elimination Systems (단상 전원 고조파 제거 시스템을 위한 기준전류 생성회로에 대한 연구)

  • Jung Done-youl;Park Chong-yeon;Kim Sang-hun;Choi Won-ho
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.54 no.7
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    • pp.335-342
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    • 2005
  • This paper presents a circuit to generate the current reference signal for single-phase harmonic elemination systems. Some of conventional methods for the current reference signal generation based on neural network algorithms. It requires complex circuitry to implement. the simplest method is to use analog filters. but it is difficult to obtain good current reference signals. So, we propose the harmonic detection circuit using GIC(Generalized Impedance Converter) for the purpose of low cost ,simple circuitry and high performance, Simulation and experimental results verify that the proposed circuit has better harmonic detection performance than conventional circuit.