Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Voltage Island Partitioning Based Floorplanning Algorithm

  • Kim, Jae-Hwan (Dept. of Electronics and Computer Engineering, Hanyang University) ;
  • Chong, Jong-Wha (Dept. of Electronics and Computer Engineering, Hanyang University)
  • Received : 2012.08.08
  • Published : 2012.09.30
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Abstract

As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.

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References

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