• Information and Communications Magazine
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• v.9 no.9
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• pp.72-85
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• 1992

The throughput requirement for many digital signal processing is such that multiple processing units are essential for real-time implementation. Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of function units. The research on a very high throughput VLSI architecture for digital signal processing applications requires the development of an algorithm, decomposition scheme which can minimize data communication requirements as well as minimize computational complexity. The objectives of the research are to investigate computationally efficient algorithms for solution of the class of problems which can be modeled as DLSI systems or adaptive system, and develop VLSI architectures and associated multiprocessor systems which can be used to implement these algorithms in real-time. A new VLSI architecture for real-time 2-D digital signal processing applications is proposed in this research. This VLSI architecture extends the concept of having a single processing units in a chip. Because this VLSI architecture has the advantage that the complexity and the number of computations per input does not increase as the size of the input data in increased, it can process very large 2-D date in near real-time.

• Proceedings of the Korean Society for Quality Management Conference
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• 1998.11a
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• pp.393-403
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• 1998

The advent of very large scale integration(VLSI) has had a tremendous impact on the design of fault-tolerant circuits and systems. The increasing density, decreasing power consumption, and decreasing costs of integrated circuits, due in part to VLSI, have made it possible and practical to implement the redundancy approaches used in fault-tolerant computing. The purpose of this paper is to study the many aspects of designing fault-tolerant systems in a VLSI environment. First, we expound upon the opportunities and problemes presented by VLSI technology. Second, we consider in detail the importance of design mistakes, common-mode failures, and transient faults in VLSI. Finally, we examine the techniques available to implement redundancy using VLSI and the problems associated with these techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.702-708
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• 2000

In this paper, we designed one-dimensional VLSI array with optimal pipeline period for high speed processing fractal image compression. The algorithm is derived which is suitable for VLSI array from axed block partition algorithm. Also the algorithm satisfies high quality of image and high compression-ratio. The designed VLSI array has optimal pipeline relied because the required processing time of PEs is distributed as same as possible. As this result, we can improve the processing speed up to about 3 times. The number of input/output pins can be reduced by sharing the input/output and arithmetic unit of the domain blocks and the range blocks.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.22 no.53
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• pp.111-120
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• 1999

The advent of very large scale integration(VLSI) has had a tremendous impact on the design of fault-tolerant circuits and systems. The increasing density, decreasing power consumption, and decreasing costs of integrated circuits, due in part to VLSI, have made it possible and practical to implement the redundancy approaches used in fault-tolerant computing. The purpose of this paper is to study the many aspects of designing fault-tolerant systems in a VLSI environment. First, we expound upon the opportunities and problems presented by VLSI technology. Second, we consider in detail the importance of design mistakes, common-mode failures, and transient faults in VLSI. Finally, we examine the techniques available to implement redundancy using VLSI and the promlems associated with these techniques.

• Journal of the Korea Computer Industry Society
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• v.5 no.4
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• pp.511-516
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• 2004

In this paper, we propose a low-power motion-estimation VLSI architecture based on systolic array using partial norms and spatial correlation. Our approach reduces computational load based on eliminating invalid block-matching points.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.708-712
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• 1987

This paper deals with minimizing layout area of VLSI design. A long wire in a VLSI layout causes delay which can be reduced by using a driver. There can be significant area increase when many drivers are introduced in a layout. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area optimal embeddings for VLSI graphs in rectangles of several aspect ratios.

• Proceedings of the KIEE Conference
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• 1983.07a
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• pp.247-249
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• 1983

분 논문에서는 순차제어기 설계 과정을 전산화함과 동시에 여러 종류의 순차 제어 방식에도 일반적으로 적용될 수 있는 VLSI회로 설계법을 제안하고 있다. 특히 VLSI설계에 적합한 회로를 구성하기 위해 최소 구성의 기억 소자를 사용하여 이에 맞는 설계 프로그램을 개발하여 응용 결과를 기존의 방법과 비교하여 보았다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.2
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• pp.7-15
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• 1983

In recent years, the logic circuits of high function have been developed to VLSI by the radical advancement of semi-conductor technologies. Under the above influence, it has become possible to design the special VLSI chips for high speed of numerical value processing, wide-band, image processing, etc. And, the development of the VLSI from various kinds of software package has become quite possible. This paper is to propose the technical skill of hardware design about general software package (BMD). The decrease of speed of former statistics processing caused by depending on software only is improved by hardware. In regard of design algorithm, the main system will be able to be established by considering of special feature of statistics. As a result, the complexity of software package is excluded by hardware. And, the efficiency is improved by high speed processing.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.433-442
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• 1995

This paper presents an improved VLSI implementation of a parallel sorter to achieve O(Ν) time complexity. Many fast VLSI sort algorithms have been proposed for sorting N elements in O(log Ν) time. However, most such algorithms proposed have complex network structure without considering data input and output time. They are also very difficult to expand or to use in real applications. After analyzing the chip area and time complexity of several parallel sort algorithms with overlapping data input and output time, the most effective algorithm, the rebound sort algorithm, is implemented in VLSI with some improvements. To achieve O(Ν) time complexity, an improved rebound sorter is able to sort 8 16-bits records on a chip. And it is possible to sort more than 8 records by connecting chips in a chain vertically.

• 전기의세계
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• v.34 no.8
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• pp.489-496
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• 1985

VLSI기술의 독특한 특징들은 이에 맞는 VLSI 지향적 아키텍쳐를 요구하게 된다. 이러한 아키텍쳐들은 영상신호 처리에 있어 중요한 실시간 처리를 위한 병렬처리 및 pipeline처리에도 잘 조화되어 고속영상신호 처리를 위한 시스템에서 VLSI기술이 필수적으로 사용 되어야 함을 알 수 있다. 현재 고속 영상신호 처리를 위한 VLSI 구조로 화면의 병렬성에 근거를 둔 CLA(Cellular Logic Array) 및 이의 단점을 보완한 피라밋 구조가 활말히 연구되고 있으나 거대한 양의 하드웨어 및 주변 시스템의 요구로 그 규모가 방대하여 지는 흠이 있다. 이에 반하여 화소 Kernel의 병렬성에 근거를 두는 pixel-kernel 프로세서는 영상신호 데이타의 공간의존성의 기본 단위인 Kernel을 병렬처리하고 그 거대성 및 균일성은 Pipeline 처리를 함으로써 비교적 작은 하드웨어로 높은 성능을 얻을수 있다. 또한 기존 영상 Sensor 로부터의 데이타 흐름을 중단 시키지 않고 처리할 수 있으며 기본 프로세서의 다양한 조합 방법에 의해 시스템 구조상의 유연성을 갖는다. 따라서 로보트 등의 실제적인 응용분야에서 후자의 구조가 효율적으로 사용될 것으로 전망된다. 앞으로 효과적인 pixel-Kernel 프로세서의 개발을 위해 PKF 계산구조의 연구와 함께 효과적인 Kernel 병렬성을 실현할 수 있는 VLSI 지향적 구조의 개발이 요구된다.