• Korean Journal of Remote Sensing
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• v.34 no.4
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• pp.693-702
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• 2018

With the development of data analysis methods and data processing capabilities, semantic analysis of floorplans has been actively studied. Therefore, studies for extracting text information from drawings have been conducted for semantic analysis. However, existing research that separates rasterized text from floorplan has the problem of loss of text information, because when graphic and text components overlap, text information cannot be extracted. To solve this problem, this study defines the morphological characteristics of the text in the floorplan, and classifies the class of the corresponding region by applying the class of the SIFT key points through the SVM models. The algorithm developed in this study separated text components with a recall of 94.3% in five sample drawings.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.344-350
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• 2011

Higher integrated density in 3D ICs also brings the difficulties of routing, which can cause the routing failure or re-design from beginning. Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost. In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage. This method uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation. During the synthesis, the TSV location is also under consideration. The experiments indicate that our proposed method had small difference with the estimation result got at the post-placement stage. Furthermore, the comparison of congestion maps obtained with our method and global router demonstrates that our estimation method is able to predict the congestion hot spots accurately.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.3
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• pp.217-230
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• 2009

In this paper we propose a new CBL-based floorplan method that accommodates pre-placed blocks. We identify the problem of the previous CBL-based pre-placed block floorplan method, and suggest the solution method of this problem. In our method, CBLs consisting of only free blocks are perturbed and maintained during the simulated annealing. Pre-placed blocks are inserted during packing in such a way that the topology of the CBL after insertion of a pre-placed block resembles the topology before insertion. Thus, even with the inclusion of pre-placed blocks, the searching effort via simulated annealing yields acceptable results. Experimental results show that our floorplan method places pre-placed blocks effectively and efficiently.

• International conference on construction engineering and project management
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• 2022.06a
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• pp.792-799
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• 2022

Building Information Modeling (BIM) technology is a key component of modern construction engineering and project management workflows. As-is BIM models that represent the spatial reality of a project site can offer crucial information to stakeholders for construction progress monitoring, error checking, and building maintenance purposes. Geometric methods for automatically converting raw scan data into BIM models (Scan-to-BIM) often fail to make use of higher-level semantic information in the data. Whereas, semantic segmentation methods only output labels at the point level without creating object level models that is necessary for BIM. To address these issues, this research proposes a hybrid semantic-geometric approach for clutter-resistant floorplan generation from laser-scanned building point clouds. The input point clouds are first pre-processed by normalizing the coordinate system and removing outliers. Then, a semantic segmentation network based on PointNet++ is used to label each point as ceiling, floor, wall, door, stair, and clutter. The clutter points are removed whereas the wall, door, and stair points are used for 2D floorplan generation. A region-growing segmentation algorithm paired with geometric reasoning rules is applied to group the points together into individual building elements. Finally, a 2-fold Random Sample Consensus (RANSAC) algorithm is applied to parameterize the building elements into 2D lines which are used to create the output floorplan. The proposed method is evaluated using the metrics of precision, recall, Intersection-over-Union (IOU), Betti error, and warping error.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1021-1024
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• 1998

Computer-aided design of VLSI circuits is usually carried out in three synthesis steps; high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further kroken into a few optimization problems. In this paper we study the area minimization problem in floorplanning(also known as the floorplan sizing problem). We propose the area minimization algorithms for general floorplans.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.28-36
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• 2009

Sequence-Pair(SP) model represents the topological relation between modules. In general, SP model based floorplanners search solutions using Simulated-Annealing(SA) algorithm. Several SA based floorplanning techniques using SP model have been published. To improve the performance of those techniques they tried to improve the speed for evaluation function for SP model, to find better scheduling methods and perturb functions for SA. In this paper we propose a two phase SA based algorithm. In the first phase, white space between modules is reduced by applying compaction technique to the floorplan obtained by an SP. From the compacted floorplan, the corresponding SP is determined. Solution space has been searched by changing the SP in the SA framework. When solutions converge to some threshold value, the first phase of the SA based search stops. Then using the typical SA based algorithm, ie, without using the compaction technique, the second phase of our algorithm continues to find optimal solutions. Experimental results with MCNC benchmark circuits show that how the proposed technique affects to the procedure for SA based floorplainning algorithm and that the results obtained by our technique is better than those obtained by existing SA-based algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.134-139
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• 2006

In this paper we present the Low-Power Bus Driven Floorplan(BDF) in which the bus power consumption is minimized by using a new cost function. The previously reported BDF has used the cost function which minimizes only the chid and the bus area. However, such a cost function may not consider the bus power consumption determined by the topology of a bus in case of the segmented bus design. In this paper, we formulate a new cost function which. reflects the communication frequency and the real distance between blocks in a bus to model the bus power consumption. For the Low-Power BDF with the new cost function, the experimental results show the bus power consumption cost is reduced by 11.43% on the average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.61-72
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• 2005

This paper proposes a method which efficiently allocates decoupling capacitance to reduce power supply noise at the floorplan level. We observe problems of previous approach that the decoupling capacitance of each module was overestimated and the power supply noises of modules were changed by inserting additional area for decoupling capacitance, and then suggest a new approach. And, we also present a simple heuristic method which can effectively allocate white space modules for decoupling capacitance area within more faster time instead of LP technique. Experimental results show that our approach can reduce the area of decoupling capacitance to average 7.9 percent compared with Zhao's approach in [4]. Therefore both total area and wire length of nniflm result are decreased. Also, we confirm that our approach solves well the problem caused by inserting additional area. In execution time comparison, our approach shows average 11.6 percent improvement.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.1-8
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• 2014

As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.