• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.48-57
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• 2020

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1021-1030
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• 2010

In the sensor network, many tiny nodes construct Ad-Hoc network using wireless interface. As this type of system consists of thousands of nodes, managing each sensor node in real world after deploying them is very difficult. In order to install the sensor network successfully, it is necessary to verify its software using a simulator beforehand. In fact Sensor network simulators require high fidelity and timing accuracy to be used as a design, implementation, and evaluation tool of wireless sensor networks. Cycle-accurate, instruction-level simulation is the known solution for those purposes. In this paper, we developed an instruction-level sensor network simulator for Telos sensor node as named TeloSlM. It consists of MSP430 and CC2420. Recently, Telos is the most popular mote because MSP430 can consume the minimum energy in recent motes and CC2420 can support Zigbee. So that TeloSlM can provide the easy way for the developers to verify software. It is cycle-accurate in instruction-level simulator that is indispensable for OS and the specific functions and can simulate scalable sensor network at the same time. In addition, TeloSlM provides the GUI Tool to show result easily.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.479-488
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• 2001

As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.2
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• pp.103-110
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• 2010

In this paper, a new mode changeable asymmetric full bridge dc/dc converter is proposed to solve the freewheeling current problem of the conventional zero voltage switching(ZVS) phase shift full bridge(PSFB) dc/dc converter of low output voltage and high output current applications. The proposed converter is operated as an asymmetric full bridge converter when the duty cycle is less than 50% and active clamp full bridge converter when the duty cycle is greater than 50%. As a result, since its freewheeling current is eliminated, the conduction loss is lower than that of the conventional ZVS PSFB dc/dc converter. Moreover, ZVS of all power switches can be ensured along a wide load ranges and output current ripple is very small. Therefore, high efficiency of the proposed converter can be achieved. Especially since its operation mode is changed to the active clamp full bridge converter during hold up time and can be operated with 50~100% duty ratio, it can produce the stable output voltage along wide input voltage range. The operational principles, theoretical analysis and design considerations are presented. To confirm the operation, validity and features of the proposed converter, experimental results from a 1.2kW($400V_{dc}/12V_{dc}$) prototype are presented.

• International Journal of Highway Engineering
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• v.12 no.4
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• pp.17-28
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• 2010

A climbing lane is installed to separate low-speed traffic from high-speed traffic if drastic traffic capacity reduction is expected due to a large number of vehicles that slow down in the upward section. Existing studies on climbing lanes have focused on the designation, location of starting and ending points, and installation method of climbing lane with regard to road design standards. However, in terms of traffic operation, it was known that the climbing lanes cause traffic congestion due to the increase of traffic volumes. In this regard, this study aims to establish traffic operational guidance as to how much effects temporary closure of climbing lanes can have on traffic improvement according to the volume-capacity ratio, grade, and composition of trucks. A test section of simulated climbing lane was selected in Nakdong JC bound for Masan(136.9K~133.3K, 3.6km, 3.7%) on Jungbunaeryuk expressway to conduct VISSIM analyses, microscopic traffic simulation based on such control variables as traffic volume(v/c), grade and the trucks ratio. As a result of the analyses, it has been found that v/c and the ratio of trucks are the key variables for efficient traffic management of climbing lanes in order to relieve traffic congestion via climbing lane. If ratio of trucks are more than 50% and when v/c would be 0.8, both climbing lane would be closed and non-operated regardless of grade and ratio of trucks when v/c is 1.0. With the increased traffic due to a five-day work week system, continued peak hours during the weekday, increased and various patterns of congestion on expressway, this study would be expected to contribute to facilitating researches on flexible operational standards for road facilities.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.323-335
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• 2015

Mobile healthcare is a fusion of information technology and biotechnology and is a new type of health management service to keep people's health at anytime and anywhere without regard to time and space. The WBAN(Wireless Body Area Network) technology that collects bio signals and the data analysis and monitoring technology using mobile devices are essential for serving mobile healthcare. WBAN consisting of users with mobile devices meet another WBAN during movement, WBANs transmit data to the other media. Because of WBAN conflict, several nodes transmit data in same time slot so a collision will occur, resulting in the data transmission being failed and need more energy for re-transmission. In this thesis, we proposed a MAC protocol for WBAN with mobility to solve these problems. First, we proposed a superframe structure for WBAN. The proposed superframe consists of a TDMA(Time Division Muliple Access) based contention access phase with which a node can transmit data in its own time slot and a contention phase using CSMA/CA algorithm. Second, we proposed a network merging algorithm for conflicting WBAN based on the proposed MAC protocol. When a WBAN with mobility conflicts with other WBAN, data frame collision is reduced through network reestablishment. Simulations are performed using a Castalia based on the OMNeT++ network simulation framework to estimate the performance of the proposed superframe and algorithms. We estimated the performance of WBAN based on the proposed MAC protocol by comparing the performance of the WBAN based on IEEE 802.15.6. Performance evaluation results show that the packet transmission success rate and energy efficiency are improved by reducing the probability of collision using the proposed MAC protocol.

• Tunnel and Underground Space
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• v.15 no.2 s.55
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• pp.119-128
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• 2005

Although the evaluation of the mechanical properties and behavior of jointed rock masses is very important for the design of tunnel and underground openings, it has always been considered the most difficult problem. One of the difficulties in describing the rock mass behavior is the selection of the appropriate constitutive model. This limitation may be overcome with the progress in discrete element software such as PFC, which does not need the user to prescribe a constitutive model for rock mass. In this paper, a 30\;m\;\times\;30\;m\;\times\;30\;m m jointed rock mass of road tunnel site was analyzed. h discrete fracture network was developed from the joint geometry obtained from core logging and surface survey. Using the discontinuities geometry from the DFN model, PFC simulations were carried out, starting with the intact rock and systematically adding the joints and the stress-strain response was recorded for each case. With the stress-strain response curves, the mechanical properties of jointed rock masses were determined. As expected, the presence of joints had a pronounced effect on mechanical properties of the rock mass. More importantly, getting the mechanical response of the PFC model doesn't require a user specified constitutive model.

• Korean Journal of Soil Science and Fertilizer
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• v.39 no.1
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• pp.29-37
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• 2006

In remediation of the contaminated soil, it requires to select at least more than two remediation technologies depending on the fate and transport phenomena through complicated reactions in soil matrix. Therefore, methodologies related to develop the integrated remediation technology were reviewed for agricultural soils contaminated with heavy metals. Pneumatic fracturing is necessary to implement deficiency because soil washing is not effective to remove heavy metals in the subsurface soil. But it needs to evaluate the characteristics such as essential data and factors of designated technology in order to effectively apply them in the site. In the remediation site, the important soil physical and chemical factors to be considered are hydrology, porosity, soil texture and structure, types and concentrations of the contaminants, and fate and its transport properties. However, the integrated technology can be restrictive by advective flux in the area which remediation is highly effective although both soil washing and pneumatic fracturing were applied simultaneously in the site. Therefore, we need to understand flow pathways of the target contaminants in the subsurface soils, that includes kinetic desorption and flux, predictive simulation modeling, and complicated reaction in heterogenous soil.

• Journal of Korean Society of Transportation
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• v.21 no.3
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• pp.47-56
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• 2003

Considering the high density developments along the major traffic corridors in Seoul, transit-oriented street designs will be a very effective to control traffic congestion along the corridors. For testing the effectiveness, we selected. for our case study, Kangnam Street, which is one of the most highly developed corridors in Seoul The traffic study on Kangnam street in 2000 shows that the daily average bus speed is 11.73km/h, which is 5km/h lower than the auto speed. The Central Bus Lane system was applied on the Kangnam street to test impact on bus speed as well as auto speed. Simulation results show that with Central Bus Lane have been improved the travel speeds of bus as well as auto on Kangnam street from 14.4km/hr to 35.0km/hr and from 25.1km/hr to 26.1km/hr, respectively. The bus market share increases about 6-8 percentages. Especially, 13.4% of bus users are increased for long-distance trips.