• Journal of Electrical Engineering and Technology
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• 제13권1호
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• pp.387-392
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• 2018

Static characteristics of SiC (silicon carbide) lateral p-i-n diodes implemented on semi-insulating substrate without an epitaxial layer are inVestigated. On-axis SiC HPSI (high purity semi-insulating) and VDSI (Vanadium doped semi-insulating) substrates are used to fabricate the lateral p-i-n diode. The space between anode and cathode ($L_{AC}$) is Varied from 5 to $20{\mu}m$ to inVestigate the effect of intrinsic-region length on static characteristics. Maximum breakdown Voltages of HPSI and VDSI are 1117 and 841 V at $L_{AC}=20{\mu}m$, respectiVely. Due to the doped Vanadium ions in VDSI substrate, diffusion length of carriers in the VDSI substrate is less than that of the HPSI substrate. A forward Voltage drop of the diode implemented on VDSI substrate is 12 V at the forward current of $1{\mu}A$, which is higher than 2.5 V of the diode implemented on HPSI substrate.

• Journal of Power Electronics
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• 제11권3호
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• pp.381-388
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• 2011

This article presents the development of a model for SiC power diodes based on the physics of the semiconductor. The model is able to simulate the behavior of the dynamics of the charges in the N- region based on the stored charge inside the SiC power diode, depending on the working regime of the device (turn-on, on-state, and turn-off). The optimal individual calculation of the ambipolar diffusion length for every phase of commutation allows for solving the ambipolar diffusion equation (ADE) using a very simple approach. By means of this methodology development a set of differential equations that models the main physical phenomena associated with the semiconductor power device are obtained. The model is developed in Pspice with acceptable simulation times and without convergence problems during its implementation.

• KIEE International Transactions on Electrophysics and Applications
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• 제11C권4호
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• pp.99-106
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• 2001

An overview of Silicon Carbide (SiC) Static Induction Transistor (SIT) development is presented. Basic conduction mechanisms are introduced and discussed, including ohmic, exponential, and space charge limited conduction (SCLC) mechanisms. Additionally, the impact of velocity saturation and temperature effects on SCLC are reviewed. The small-signal model, breakdown voltage, power density, and different gate structures are also discussed, before a final review of published SiC SIT results. Published S-band (3-4 GHz) results include 9.5 dB of gain and output power of 120 W, and L-band (1.3 GHz) results include 400 W output power, 7.7 dB of gain, and power density of 16.7 W/cm.

• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.101-105
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• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.17-19
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• 2004

The electrical properties of gate oxides grown in two different processes, which are in 10% nitrous oxide($N_2O$) and in dry oxygen, have been experimentally investigated and compared. It has been observed that the $SiC-SiO_2$ interface-trap density(Dit) measured in nitrided gate oxide has been tremendously reduced, compared to the density obtained from gate oxide grown in dry oxygen. The beneficial effects of nitridation on gate oxides also have been demonstrated in the values of total near interface-trap density and of forward-bias breakdown field. The reasons of these improvements have been explained.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.3-6
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• 2004

반도체 디자인, 공정 기술 및 패기지 기술의 발달에 따라 전력용 반도체는 소형화, 고성능화, 지능화하고 있다. 고속 구동이 용이한 때문에 MOSFET이나 IGBT등의 MOS-gate형 전력 반도체의 발전이 두드려지며, trench, charge balance, NPT 기술등이 패키지 기술과 더불어 이를 위한 주요 기술이 될것으로 보인다. SiC나 GaN등의 Wide Band Gap 물질들을 사용한 차세대 전력 반도체 연구도 활발히 진행되고 있다.

• Journal of Power Electronics
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• 제12권1호
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• pp.19-23
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• 2012

This paper presents a practical methodology for realistic simulation on reverse characteristics of Wide Bandgap (WBG) SiC and GaN p-n junctions. The adjustment on certain physic-based model parameters, such as the trap density and photo-generation for SiC junction, and impact ionization coefficients and critical field for GaN junction are described. The adjusted parameters were used in Synopsys Medici simulation to obtain a realistic p-n junction avalanche breakdown voltage. The simulation results were verified through benchmarking against independent data reported by others.

• 한국결정성장학회지
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• 제33권2호
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• pp.45-53
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• 2023

4H-SiC 기판 위의 Si 성장은 전력 반도체, 바이폴라 접합 트랜지스터 및 광전자 공학에서 매우 유용한 재료로서 광범위한 응용 분야를 가지고 있다. 그러나 Si와 4H-SiC 사이에 약 20 %의 격자 불일치로 인해 4H-SiC에서 매우 양질의 결정 Si를 성장시키는 것은 상당히 어렵다. 본 논문에서는 혼합 소스 수소화물 기상 에피택시 방법을 이용하여 4H-SiC 기판에서 성장한 Al 관련 나노 구조체 클러스터에 의한 육각형 Si 에피층의 성장을 보고한다. 4H-SiC 기판 위에 육각형 Si 에피층을 성장시키기 위해 먼저 Al 관련 나노 구조체 클러스터가 형성되고 Si 원자를 흡수하여 육각형 Si 에피층이 형성되는 과정을 관찰하였다. Al 관련 나노 구조체 클러스터와 육각형 Si 에피층에 대하여 FE-SEM 및 라만 스펙트럼 결과로부터 육각형 Si 에피층은 일반적인 입방정계 Si 구조와 다른 특성을 가지는 것으로 판단된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.187-187
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• 2007

This paper presents the electrical properties of SiGe HBTs designed with bottom collector and single metal layer structure for RF power amplifier. Base layer was formed with graded-SiGe/Si structures and the collector place to the bottom of the device. Bottom collector and single metal layer structures could significantly simplify the fabrication process. We studied about the influence of SiGe base thickness, number of emitter fingers and temperature dependence (< $200^{\circ}C$) on electrical properties. The feasible application in 1~2GHz frequency from measured data $BV_{CEO}$ ~10V, $f_r$~14 GHz, ${\beta\simeq}110$, NF~1 dB using packaged SiGe HBTs. We will discuss the temperature dependent current flow through the e-b, b-c junctions to understand stability and performance of the device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.101-102
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• 2005

SiC lateral power semiconductor device has high breakdown voltage and low on-state voltage drop due to the material characteristics. And, because the high breakdown voltage can be obtained, RESURF technique is mostly used in silicon power semiconductor devices. In this paper, we presents the electrical characteristics of the 4H-SiC RESURF LDMOSFET as a function of the epi-layer length, concentration and thickness. 240~780V of breakdown voltage can be obtained as a function of epi-layer length and thickness with same epi-layer concentration.